commit 3b6b0e42f04c84091669e6107362a437f70df9ca
author Venkatraman Govindaraju <venkatra@cs.wisc.edu> Sat Mar 01 02:28:34 2014 +0000
committer Venkatraman Govindaraju <venkatra@cs.wisc.edu> Sat Mar 01 02:28:34 2014 +0000
tree 89bec37c8193becf4273ea33f09ff8bffdc958e9
parent 6f2e08c8e1827268c59f572c1bbe2ab8ecc9d339

[Sparc] 80 column rule. No functionality change.

llvm-svn: 202565

llvm/lib/Target/Sparc/SparcISelLowering.cpp

diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 632cc2b..d52cf26 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2649,7 +2649,8 @@
 }
 
 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
-  assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) && "invalid");
+  assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
+         && "invalid opcode");
 
   if (Op.getValueType() == MVT::f64)
     return LowerF64Op(Op, DAG, Op.getOpcode());