AMDGPU : Add a function to enable and disable IEEEBit for SC and shader
respectively.
Differential Revision: http://reviews.llvm.org/D25789
llvm-svn: 284655
diff --git a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
index 723e3c2..28d065e 100644
--- a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
@@ -2,7 +2,7 @@
; GCN-LABEL: {{^}}test_default_si:
; GCN: FloatMode: 192
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
define void @test_default_si(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -11,7 +11,7 @@
; GCN-LABEL: {{^}}test_default_vi:
; GCN: FloatMode: 192
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -20,7 +20,7 @@
; GCN-LABEL: {{^}}test_f64_denormals:
; GCN: FloatMode: 192
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -29,7 +29,7 @@
; GCN-LABEL: {{^}}test_f32_denormals:
; GCNL: FloatMode: 48
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -38,7 +38,7 @@
; GCN-LABEL: {{^}}test_f32_f64_denormals:
; GCN: FloatMode: 240
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -47,13 +47,41 @@
; GCN-LABEL: {{^}}test_no_denormals
; GCN: FloatMode: 0
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
ret void
}
+; GCN-LABEL: {{^}}kill_gs_const:
+; GCN: IeeeMode: 0
+define amdgpu_gs void @kill_gs_const() {
+main_body:
+ %0 = icmp ule i32 0, 3
+ %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
+ call void @llvm.AMDGPU.kill(float %1)
+ %2 = icmp ule i32 3, 0
+ %3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
+ call void @llvm.AMDGPU.kill(float %3)
+ ret void
+}
+
+; GCN-LABEL: {{^}}kill_vcc_implicit_def:
+; GCN: IeeeMode: 0
+define amdgpu_ps void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
+entry:
+ %tmp0 = fcmp olt float %13, 0.0
+ call void @llvm.AMDGPU.kill(float %14)
+ %tmp1 = select i1 %tmp0, float 1.0, float 0.0
+ call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
+ ret void
+}
+
+
+declare void @llvm.AMDGPU.kill(float)
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
attributes #0 = { nounwind "target-cpu"="tahiti" }
attributes #1 = { nounwind "target-cpu"="fiji" }
attributes #2 = { nounwind "target-features"="+fp64-denormals" }