[RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.
Differential Revision: https://reviews.llvm.org/D66973
llvm-svn: 372106
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
index 0046b59..2887522 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -197,11 +197,11 @@
;
; RV64IFD-LABEL: fcmp_ord:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, a1
-; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0
-; RV64IFD-NEXT: feq.d a0, ft0, ft0
-; RV64IFD-NEXT: and a0, a0, a1
+; RV64IFD-NEXT: fmv.d.x ft1, a1
+; RV64IFD-NEXT: feq.d a0, ft1, ft1
+; RV64IFD-NEXT: feq.d a1, ft0, ft0
+; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
@@ -397,11 +397,11 @@
;
; RV64IFD-LABEL: fcmp_uno:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d.x ft0, a1
-; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0
-; RV64IFD-NEXT: feq.d a0, ft0, ft0
-; RV64IFD-NEXT: and a0, a0, a1
+; RV64IFD-NEXT: fmv.d.x ft1, a1
+; RV64IFD-NEXT: feq.d a0, ft1, ft1
+; RV64IFD-NEXT: feq.d a1, ft0, ft0
+; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: ret
%1 = fcmp uno double %a, %b