Tighten operand checking on CPS instructions.
llvm-svn: 137172
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index dc19f46..34b3e62 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -1390,6 +1390,7 @@
let Inst{4-0} = mode;
}
+let DecoderMethod = "DecodeCPSInstruction" in {
let M = 1 in
def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
"$imod\t$iflags, $mode">;
@@ -1398,6 +1399,7 @@
let imod = 0, iflags = 0, M = 1 in
def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
+}
// Preload signals the memory system of possible future data/instruction access.
// These are for disassembly only.
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d7b8856..a3fa138 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -83,6 +83,8 @@
const void *Decoder);
static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
@@ -1139,6 +1141,9 @@
unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
unsigned mode = fieldFromInstruction32(Insn, 0, 5);
+ // imod == '01' --> UNPREDICTABLE
+ if (imod == 1) return false;
+
if (M && mode && imod && iflags) {
Inst.setOpcode(ARM::CPS3p);
Inst.addOperand(MCOperand::CreateImm(imod));
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
index d3a75cb..10748e9 100644
--- a/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
+++ b/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
# invalid imod value (0b01)
0xc0 0x67 0x4 0xf1
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
index cc6062e..5202217 100644
--- a/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
+++ b/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
# invalid (imod, M, iflags) combination
0x93 0x1c 0x02 0xf1