[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6
Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.
We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.
Depends on D4111
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4112
llvm-svn: 210787
diff --git a/llvm/test/CodeGen/Mips/analyzebranch.ll b/llvm/test/CodeGen/Mips/analyzebranch.ll
index 8ec5d93..d9ad0f8 100644
--- a/llvm/test/CodeGen/Mips/analyzebranch.ll
+++ b/llvm/test/CodeGen/Mips/analyzebranch.ll
@@ -1,9 +1,25 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
+; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
+; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
+; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
+; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
+; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
+; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
define double @foo(double %a, double %b) nounwind readnone {
entry:
-; CHECK: bc1f $BB
-; CHECK: nop
+; ALL-LABEL: foo:
+
+; FCC: bc1f $BB
+; FCC: nop
+
+; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
+; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
+; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
+; GPR: cmp.olt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
+; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
+; GPR: bnez $[[GPRCC]], $BB
%cmp = fcmp ogt double %a, 0.000000e+00
br i1 %cmp, label %if.end6, label %if.else
@@ -25,8 +41,17 @@
define void @f1(float %f) nounwind {
entry:
-; CHECK: bc1f $BB
-; CHECK: nop
+; ALL-LABEL: f1:
+
+; FCC: bc1f $BB
+; FCC: nop
+
+; GPR: mtc1 $zero, $[[Z:f[0-9]]]
+; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]]
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
+; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
+; GPR: beqz $[[GPRCC]], $BB
+
%cmp = fcmp une float %f, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end
diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll
index a136557..311b830 100644
--- a/llvm/test/CodeGen/Mips/fpbr.ll
+++ b/llvm/test/CodeGen/Mips/fpbr.ll
@@ -1,9 +1,25 @@
-; RUN: llc < %s -march=mipsel | FileCheck %s
+; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC
+; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
+; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC
+; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
define void @func0(float %f2, float %f3) nounwind {
entry:
-; CHECK: c.eq.s
-; CHECK: bc1f
+; ALL-LABEL: func0:
+
+; 32-FCC: c.eq.s $f12, $f14
+; 64-FCC: c.eq.s $f12, $f13
+; FCC: bc1f $BB0_2
+
+; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
+; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
+; FIXME: We ought to be able to transform not+bnez -> beqz
+; GPR: not $[[GPRCC]], $[[GPRCC]]
+; GPR: bnez $[[GPRCC]], $BB0_2
+
%cmp = fcmp oeq float %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@@ -25,8 +41,18 @@
define void @func1(float %f2, float %f3) nounwind {
entry:
-; CHECK: c.olt.s
-; CHECK: bc1f
+; ALL-LABEL: func1:
+
+; 32-FCC: c.olt.s $f12, $f14
+; 64-FCC: c.olt.s $f12, $f13
+; FCC: bc1f $BB1_2
+
+; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
+; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
+; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
+; GPR: bnez $[[GPRCC]], $BB1_2
+
%cmp = fcmp olt float %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@@ -44,8 +70,18 @@
define void @func2(float %f2, float %f3) nounwind {
entry:
-; CHECK: c.ole.s
-; CHECK: bc1t
+; ALL-LABEL: func2:
+
+; 32-FCC: c.ole.s $f12, $f14
+; 64-FCC: c.ole.s $f12, $f13
+; FCC: bc1t $BB2_2
+
+; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12
+; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
+; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
+; GPR: beqz $[[GPRCC]], $BB2_2
+
%cmp = fcmp ugt float %f2, %f3
br i1 %cmp, label %if.else, label %if.then
@@ -63,8 +99,19 @@
define void @func3(double %f2, double %f3) nounwind {
entry:
-; CHECK: c.eq.d
-; CHECK: bc1f
+; ALL-LABEL: func3:
+
+; 32-FCC: c.eq.d $f12, $f14
+; 64-FCC: c.eq.d $f12, $f13
+; FCC: bc1f $BB3_2
+
+; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14
+; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
+; FIXME: We ought to be able to transform not+bnez -> beqz
+; GPR: not $[[GPRCC]], $[[GPRCC]]
+; GPR: bnez $[[GPRCC]], $BB3_2
+
%cmp = fcmp oeq double %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@@ -82,8 +129,18 @@
define void @func4(double %f2, double %f3) nounwind {
entry:
-; CHECK: c.olt.d
-; CHECK: bc1f
+; ALL-LABEL: func4:
+
+; 32-FCC: c.olt.d $f12, $f14
+; 64-FCC: c.olt.d $f12, $f13
+; FCC: bc1f $BB4_2
+
+; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12
+; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
+; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
+; GPR: bnez $[[GPRCC]], $BB4_2
+
%cmp = fcmp olt double %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@@ -101,8 +158,18 @@
define void @func5(double %f2, double %f3) nounwind {
entry:
-; CHECK: c.ole.d
-; CHECK: bc1t
+; ALL-LABEL: func5:
+
+; 32-FCC: c.ole.d $f12, $f14
+; 64-FCC: c.ole.d $f12, $f13
+; FCC: bc1t $BB5_2
+
+; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12
+; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12
+; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
+; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
+; GPR: beqz $[[GPRCC]], $BB5_2
+
%cmp = fcmp ugt double %f2, %f3
br i1 %cmp, label %if.else, label %if.then