| commit | 3d59e388ca252615beb573768015d32526fd1d56 | [log] [tgz] |
|---|---|---|
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | Fri May 24 18:18:51 2019 +0000 |
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | Fri May 24 18:18:51 2019 +0000 |
| tree | 564d416539423a35d470582ce1a05c7d56a7fd13 | |
| parent | 21efe2afed7b743f37780f39b090af6145b4d527 [diff] |
AMDGPU: Activate all lanes when spilling CSR VGPR for SGPR spills If some lanes weren't active on entry to the function, this could clobber their VGPR values. llvm-svn: 361655