commit 3f18603c522c80b67db57a42bda01c6525d1acc2
author Tim Northover <tnorthover@apple.com> Tue Oct 18 20:03:45 2016 +0000
committer Tim Northover <tnorthover@apple.com> Tue Oct 18 20:03:45 2016 +0000
tree 9f10f052cfa48b35aaaa99266682062bb5acc2d5
parent 0f7f030c44f254d359eb89eb2810a8693db8881a

GlobalISel: translate memcpy intrinsics.

llvm-svn: 284525

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 155a39a..e073717 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -358,6 +358,26 @@
   return true;
 }
 
+bool IRTranslator::translateMemcpy(const CallInst &CI) {
+  LLT SizeTy{*CI.getArgOperand(2)->getType(), *DL};
+  if (cast<PointerType>(CI.getArgOperand(0)->getType())->getAddressSpace() !=
+          0 ||
+      cast<PointerType>(CI.getArgOperand(1)->getType())->getAddressSpace() !=
+          0 ||
+      SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
+    return false;
+
+  SmallVector<CallLowering::ArgInfo, 8> Args;
+  for (int i = 0; i < 3; ++i) {
+    const auto &Arg = CI.getArgOperand(i);
+    Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
+  }
+
+  MachineOperand Callee = MachineOperand::CreateES("memcpy");
+
+  return CLI->lowerCall(MIRBuilder, Callee,
+                        CallLowering::ArgInfo(0, CI.getType()), Args);
+}
 
 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
                                            Intrinsic::ID ID) {
@@ -370,6 +390,8 @@
   case Intrinsic::ssub_with_overflow: Op = TargetOpcode::G_SSUBO; break;
   case Intrinsic::umul_with_overflow: Op = TargetOpcode::G_UMULO; break;
   case Intrinsic::smul_with_overflow: Op = TargetOpcode::G_SMULO; break;
+  case Intrinsic::memcpy:
+    return translateMemcpy(CI);
   }
 
   LLT Ty{*CI.getOperand(0)->getType(), *DL};