commit 40864b690bf566900ee251eb6559418776bd33b7
author Elena Demikhovsky <elena.demikhovsky@intel.com> Mon Aug 05 08:52:21 2013 +0000
committer Elena Demikhovsky <elena.demikhovsky@intel.com> Mon Aug 05 08:52:21 2013 +0000
tree 0d5420fe7b84d8369c8e4abba4f805cc6524c7c4
parent c5244512c83f2eb7234b3e6afdeea5c6f942c638

AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.
Added intrinsics and tests.

llvm-svn: 187717

llvm/lib/Target/X86/X86ISelLowering.h

diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 03765c1..e09104a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -294,6 +294,10 @@
       // TESTP - Vector packed fp sign bitwise comparisons
       TESTP,
 
+      // OR/AND test for masks
+      KORTEST,
+      KTEST,
+
       // Several flavors of instructions with vector shuffle behaviors.
       PALIGNR,
       PSHUFD,
@@ -826,6 +830,7 @@
     SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, SDLoc dl,
                                    SelectionDAG &DAG) const;
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;