[Asm] Add debug tracing in table-generated assembly matcher
This adds debug tracing to the table-generated assembly instruction matcher,
enabled by the -debug-only=asm-matcher option.
The changes in the target AsmParsers are to add an MCInstrInfo reference under
a consistent name, so that we can use it from table-generated code. This was
already being used this way for targets that use deprecation warnings, but 5
targets did not have it, and Hexagon had it under a different name to the other
backends.
llvm-svn: 315445
diff --git a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
index 64ac82a..a0c06c9 100644
--- a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
@@ -13,8 +13,9 @@
using namespace llvm;
MCTargetAsmParser::MCTargetAsmParser(MCTargetOptions const &MCOptions,
- const MCSubtargetInfo &STI)
- : MCOptions(MCOptions), STI(&STI) {}
+ const MCSubtargetInfo &STI,
+ const MCInstrInfo &MII)
+ : MCOptions(MCOptions), STI(&STI), MII(MII) {}
MCTargetAsmParser::~MCTargetAsmParser() = default;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 3ba7a69..9f49e67 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -139,7 +139,7 @@
AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI) {
+ : MCTargetAsmParser(Options, STI, MII) {
IsILP32 = Options.getABIName() == "ilp32";
MCAsmParserExtension::Initialize(Parser);
MCStreamer &S = getParser().getStreamer();
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index fa7157b..73889e6 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -807,7 +807,6 @@
};
class AMDGPUAsmParser : public MCTargetAsmParser {
- const MCInstrInfo &MII;
MCAsmParser &Parser;
unsigned ForcedEncodingSize = 0;
@@ -855,7 +854,7 @@
AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser) {
+ : MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {
MCAsmParserExtension::Initialize(Parser);
if (getFeatureBits().none()) {
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 3792e10..1e6c175 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -168,7 +168,6 @@
};
class ARMAsmParser : public MCTargetAsmParser {
- const MCInstrInfo &MII;
const MCRegisterInfo *MRI;
UnwindContext UC;
@@ -581,7 +580,7 @@
ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
+ : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
MCAsmParserExtension::Initialize(Parser);
// Cache the MCRegisterInfo.
diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
index 5004736..2e1adcc 100644
--- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
+++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
@@ -83,7 +83,7 @@
public:
AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI), STI(STI), Parser(Parser) {
+ : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
MCAsmParserExtension::Initialize(Parser);
MRI = getContext().getRegisterInfo();
diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
index 9e251d2..deaa113 100644
--- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
+++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
@@ -28,6 +28,7 @@
struct BPFOperand;
class BPFAsmParser : public MCTargetAsmParser {
+
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool PreMatchCheck(OperandVector &Operands);
@@ -68,7 +69,7 @@
BPFAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI) {
+ : MCTargetAsmParser(Options, STI, MII) {
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
};
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index d901abb..d0d8b39 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -96,7 +96,6 @@
MCAsmParser &Parser;
MCAssembler *Assembler;
- MCInstrInfo const &MCII;
MCInst MCB;
bool InBrackets;
@@ -155,8 +154,8 @@
public:
HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, _STI), Parser(_Parser),
- MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
+ : MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),
+ MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
MCAsmParserExtension::Initialize(_Parser);
@@ -462,9 +461,9 @@
MCB.setLoc(IDLoc);
// Check the bundle for errors.
const MCRegisterInfo *RI = getContext().getRegisterInfo();
- HexagonMCChecker Check(getContext(), MCII, getSTI(), MCB, *RI);
+ HexagonMCChecker Check(getContext(), MII, getSTI(), MCB, *RI);
- bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
+ bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MII, getSTI(),
getContext(), MCB,
&Check);
@@ -608,7 +607,7 @@
MatchingInlineAsm))
return true;
HexagonMCInstrInfo::extendIfNeeded(
- getParser().getContext(), MCII, MCB, *SubInst);
+ getParser().getContext(), MII, MCB, *SubInst);
MCB.addOperand(MCOperand::createInst(SubInst));
if (!InBrackets)
return finishBundle(IDLoc, Out);
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
index 1394ac7..3f24c3e 100644
--- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
+++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
@@ -36,7 +36,7 @@
#include <cstdint>
#include <memory>
-namespace llvm {
+using namespace llvm;
// Auto-generated by TableGen
static unsigned MatchRegisterName(StringRef Name);
@@ -85,7 +85,7 @@
public:
LanaiAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI), Parser(Parser),
+ : MCTargetAsmParser(Options, STI, MII), Parser(Parser),
Lexer(Parser.getLexer()), SubtargetInfo(STI) {
setAvailableFeatures(
ComputeAvailableFeatures(SubtargetInfo.getFeatureBits()));
@@ -1226,5 +1226,3 @@
extern "C" void LLVMInitializeLanaiAsmParser() {
RegisterMCAsmParser<LanaiAsmParser> x(getTheLanaiTarget());
}
-
-} // end namespace llvm
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 4d6fb7f..59f78ed 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -473,7 +473,7 @@
MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, sti),
+ : MCTargetAsmParser(Options, sti, MII),
ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
sti.getCPU(), Options)) {
MCAsmParserExtension::Initialize(parser);
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 98be18b..2fbf510 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -251,7 +251,6 @@
struct PPCOperand;
class PPCAsmParser : public MCTargetAsmParser {
- const MCInstrInfo &MII;
bool IsPPC64;
bool IsDarwin;
@@ -298,7 +297,7 @@
public:
PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI), MII(MII) {
+ : MCTargetAsmParser(Options, STI, MII) {
// Check for 64-bit vs. 32-bit pointer mode.
const Triple &TheTriple = STI.getTargetTriple();
IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b0db5f4..c907f6d 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -30,6 +30,7 @@
struct RISCVOperand;
class RISCVAsmParser : public MCTargetAsmParser {
+
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
@@ -72,7 +73,7 @@
RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI) {
+ : MCTargetAsmParser(Options, STI, MII) {
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
};
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 087c037..05f78a4 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -108,7 +108,7 @@
SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, sti), Parser(parser) {
+ : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
}
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 3368078..1cc01af 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -425,7 +425,7 @@
SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, sti), Parser(parser) {
+ : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
MCAsmParserExtension::Initialize(Parser);
// Alias the .word directive to .short.
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 112af62..22ad3cb 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -68,7 +68,6 @@
};
class X86AsmParser : public MCTargetAsmParser {
- const MCInstrInfo &MII;
ParseInstructionInfo *InstInfo;
std::unique_ptr<X86AsmInstrumentation> Instrumentation;
bool Code16GCC;
@@ -923,7 +922,7 @@
X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
const MCInstrInfo &mii, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr),
+ : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
Code16GCC(false) {
// Initialize the set of available features.