commit 41e5ac4fa4a90f0d233f16d11763af68b735b8d7
author Matt Arsenault <Matthew.Arsenault@amd.com> Wed Mar 14 00:36:23 2018 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Wed Mar 14 00:36:23 2018 +0000
tree 0913b5ae2f8e22b8f104addbcdc1a8aa4520c6ed
parent e2d3ce2339682dd20f30ba14dd2cadbbedc827a4

TargetMachine: Add address space to getPointerSize

llvm-svn: 327467

llvm/lib/Target/Sparc/SparcISelLowering.cpp

diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index f120c02..2e9390a 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1450,7 +1450,7 @@
 SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
                                          const SparcSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
-  MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
+  MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0));
 
   // Instructions which use registers as conditionals examine all the
   // bits (as does the pseudo SELECT_CC expansion). I don't think it