commit 41e5ac4fa4a90f0d233f16d11763af68b735b8d7
author Matt Arsenault <Matthew.Arsenault@amd.com> Wed Mar 14 00:36:23 2018 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Wed Mar 14 00:36:23 2018 +0000
tree 0913b5ae2f8e22b8f104addbcdc1a8aa4520c6ed
parent e2d3ce2339682dd20f30ba14dd2cadbbedc827a4

TargetMachine: Add address space to getPointerSize

llvm-svn: 327467

llvm/lib/Target/X86/X86LegalizerInfo.cpp

diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index bcf0ffb..3a814d3 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -86,7 +86,7 @@
 
 void X86LegalizerInfo::setLegalizerInfo32bit() {
 
-  const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8);
+  const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
   const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
@@ -169,7 +169,7 @@
   if (!Subtarget.is64Bit())
     return;
 
-  const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8);
+  const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
   const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);