commit 41fa8582620616acff5a99f08cc83b3c5b54e9dc
author Craig Topper <craig.topper@intel.com> Fri Jul 13 22:41:50 2018 +0000
committer Craig Topper <craig.topper@intel.com> Fri Jul 13 22:41:50 2018 +0000
tree d5de14c3f103502b2c996171af5a7a6a6df0ca80
parent 445abf700d2fc75ef2ec19dee6c969bea45011d3

[X86][SLH] Add VEX and EVEX conversion instructions to isDataInvariantLoad

-Drop the intrinsic versions of conversion instructions. These should be handled when we do vectors. They shouldn't show up in scalar code.
-Add the float<->double conversions which were missing.
-Add the AVX512 and AVX version of the conversion instructions including the unsigned integer conversions unique to AVX512

Differential Revision: https://reviews.llvm.org/D49313

llvm-svn: 337066

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
index a99fa20..9f5f36b 100644
--- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -938,19 +938,25 @@
   case X86::SHRX64rm:
 
   // Conversions are believed to be constant time and don't set flags.
-  // FIXME: Add AVX versions.
-  case X86::CVTSD2SI64rm_Int:
-  case X86::CVTSD2SIrm_Int:
-  case X86::CVTSS2SI64rm_Int:
-  case X86::CVTSS2SIrm_Int:
-  case X86::CVTTSD2SI64rm:
-  case X86::CVTTSD2SI64rm_Int:
-  case X86::CVTTSD2SIrm:
-  case X86::CVTTSD2SIrm_Int:
-  case X86::CVTTSS2SI64rm:
-  case X86::CVTTSS2SI64rm_Int:
-  case X86::CVTTSS2SIrm:
-  case X86::CVTTSS2SIrm_Int:
+  case X86::CVTTSD2SI64rm: case X86::VCVTTSD2SI64rm: case X86::VCVTTSD2SI64Zrm:
+  case X86::CVTTSD2SIrm:   case X86::VCVTTSD2SIrm:   case X86::VCVTTSD2SIZrm:
+  case X86::CVTTSS2SI64rm: case X86::VCVTTSS2SI64rm: case X86::VCVTTSS2SI64Zrm:
+  case X86::CVTTSS2SIrm:   case X86::VCVTTSS2SIrm:   case X86::VCVTTSS2SIZrm:
+  case X86::CVTSI2SDrm:    case X86::VCVTSI2SDrm:    case X86::VCVTSI2SDZrm:
+  case X86::CVTSI2SSrm:    case X86::VCVTSI2SSrm:    case X86::VCVTSI2SSZrm:
+  case X86::CVTSI642SDrm:  case X86::VCVTSI642SDrm:  case X86::VCVTSI642SDZrm:
+  case X86::CVTSI642SSrm:  case X86::VCVTSI642SSrm:  case X86::VCVTSI642SSZrm:
+  case X86::CVTSS2SDrm:    case X86::VCVTSS2SDrm:    case X86::VCVTSS2SDZrm:
+  case X86::CVTSD2SSrm:    case X86::VCVTSD2SSrm:    case X86::VCVTSD2SSZrm:
+  // AVX512 added unsigned integer conversions.
+  case X86::VCVTTSD2USI64Zrm:
+  case X86::VCVTTSD2USIZrm:
+  case X86::VCVTTSS2USI64Zrm:
+  case X86::VCVTTSS2USIZrm:
+  case X86::VCVTUSI2SDZrm:
+  case X86::VCVTUSI642SDZrm:
+  case X86::VCVTUSI2SSZrm:
+  case X86::VCVTUSI642SSZrm:
 
   // Loads to register don't set flags.
   case X86::MOV8rm: