[AArch64] Add support for pre- and post-index LDPSWs.
llvm-svn: 248825
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index b3ff11d..87e6d0f 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -186,6 +186,7 @@
case AArch64::STRWui:
case AArch64::STURWi:
case AArch64::LDPSi:
+ case AArch64::LDPSWi:
case AArch64::LDPWi:
case AArch64::STPSi:
case AArch64::STPWi:
@@ -326,6 +327,8 @@
return AArch64::LDRSWpre;
case AArch64::LDPSi:
return AArch64::LDPSpre;
+ case AArch64::LDPSWi:
+ return AArch64::LDPSWpre;
case AArch64::LDPDi:
return AArch64::LDPDpre;
case AArch64::LDPQi:
@@ -383,6 +386,8 @@
return AArch64::LDRSWpost;
case AArch64::LDPSi:
return AArch64::LDPSpost;
+ case AArch64::LDPSWi:
+ return AArch64::LDPSWpost;
case AArch64::LDPDi:
return AArch64::LDPDpost;
case AArch64::LDPQi:
@@ -409,6 +414,7 @@
default:
return false;
case AArch64::LDPSi:
+ case AArch64::LDPSWi:
case AArch64::LDPDi:
case AArch64::LDPQi:
case AArch64::LDPWi:
@@ -1127,6 +1133,7 @@
case AArch64::LDURXi:
// Paired instructions.
case AArch64::LDPSi:
+ case AArch64::LDPSWi:
case AArch64::LDPDi:
case AArch64::LDPQi:
case AArch64::LDPWi:
@@ -1181,11 +1188,6 @@
int Value =
MI->getOperand(isPairedLdSt(MI) ? 3 : 2).getImm() * getMemScale(MI);
- // FIXME: The immediate in the load/store should be scaled by the size of
- // the memory operation, not the size of the register being loaded/stored.
- // This works in general, but does not work for the LDPSW instruction,
- // which defines two 64-bit registers, but loads 32-bit values.
-
// Look forward to try to find a post-index instruction. For example,
// ldr x1, [x0, #64]
// add x0, x0, #64