commit 43160e7af2451111917b10348e5a8dabcd5f80d0
author Matt Arsenault <Matthew.Arsenault@amd.com> Wed Jun 18 17:13:57 2014 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Wed Jun 18 17:13:57 2014 +0000
tree 3b1e47f7ac2adae9d2b6c7172cf4a8de94f2404a
parent dbc9aae1fba6ef3232c720314cb2430a678b36e5

R600/SI: Add intrinsics for brev instructions

llvm-svn: 211187

llvm/lib/Target/R600/AMDGPUISelLowering.h

diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.h b/llvm/lib/Target/R600/AMDGPUISelLowering.h
index 34e36d8..5be3070 100644
--- a/llvm/lib/Target/R600/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/R600/AMDGPUISelLowering.h
@@ -188,6 +188,7 @@
   BFE_I32, // Extract range of bits with sign extension to 32-bits.
   BFI, // (src0 & src1) | (~src0 & src2)
   BFM, // Insert a range of bits into a 32-bit word.
+  BREV, // Reverse bits.
   MUL_U24,
   MUL_I24,
   MAD_U24,