commit 43b8e4ed3b7bc4ebeabe1e56cd09cf1516245b10
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Nov 18 20:09:29 2013 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Nov 18 20:09:29 2013 +0000
tree 56d0e3a28ef25c4b276a0989e8b2b8f0cba169a5
parent f0b1e3a776c13c7feb9c4b563e2c57489d275135

R600/SI: Move patterns to match add / sub to scalar instructions

llvm-svn: 195034

llvm/test/CodeGen/R600/gep-address-space.ll

diff --git a/llvm/test/CodeGen/R600/gep-address-space.ll b/llvm/test/CodeGen/R600/gep-address-space.ll
index 934b5a5..4ea21dd 100644
--- a/llvm/test/CodeGen/R600/gep-address-space.ll
+++ b/llvm/test/CodeGen/R600/gep-address-space.ll
@@ -2,7 +2,7 @@
 
 define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
 ; CHECK-LABEL @use_gep_address_space:
-; CHECK: ADD_I32
+; CHECK: S_ADD_I32
   %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16
   store i32 99, i32 addrspace(3)* %p
   ret void
@@ -10,10 +10,10 @@
 
 define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind {
 ; CHECK-LABEL: @gep_as_vector_v4:
-; CHECK: V_ADD_I32
-; CHECK: V_ADD_I32
-; CHECK: V_ADD_I32
-; CHECK: V_ADD_I32
+; CHECK: S_ADD_I32
+; CHECK: S_ADD_I32
+; CHECK: S_ADD_I32
+; CHECK: S_ADD_I32
   %p = getelementptr <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
   %p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0
   %p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1
@@ -28,8 +28,8 @@
 
 define void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind {
 ; CHECK-LABEL: @gep_as_vector_v2:
-; CHECK: V_ADD_I32
-; CHECK: V_ADD_I32
+; CHECK: S_ADD_I32
+; CHECK: S_ADD_I32
   %p = getelementptr <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>
   %p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0
   %p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1