commit 43e569c95fcb30650f931d0c41cca2f373c9ba25
author Andrew Lenharth <andrewl@lenharth.org> Thu Mar 09 18:18:51 2006 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Thu Mar 09 18:18:51 2006 +0000
tree 4b16665ad46376bc82b18fe66912323400bfd8fc
parent 7e7dccd3ab7ecf4cd40a99244f40da95a68a3d1b

these are copies too

llvm-svn: 26653

llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 7089f52..c30f38a 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,11 @@
                                  unsigned& sourceReg,
                                  unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == Alpha::BIS || oc == Alpha::CPYSS || oc == Alpha::CPYST) {
+  if (oc == Alpha::BIS    || 
+      oc == Alpha::CPYSS  || 
+      oc == Alpha::CPYST  ||
+      oc == Alpha::CPYSSt || 
+      oc == Alpha::CPYSTs) {
     // or r1, r2, r2 
     // cpys(s|t) r1 r2 r2
     assert(MI.getNumOperands() == 3 &&