commit 43e8f7dacc13ab7456cadd6054b24f560a6eb47e
author Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> Wed Mar 21 12:49:07 2018 +0000
committer Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> Wed Mar 21 12:49:07 2018 +0000
tree d90b1b04d2cc64c99518e405f99b3b2060048499
parent 646ab4113f0501a0e5da0f4d10c12f3a3048f9a0

[llvm-mca] Clean up some code. NFC

Removed a couple of methods from DispatchUnit.

llvm-svn: 328094

llvm/tools/llvm-mca/Dispatch.cpp

diff --git a/llvm/tools/llvm-mca/Dispatch.cpp b/llvm/tools/llvm-mca/Dispatch.cpp
index 52968ea1..3614d4d 100644
--- a/llvm/tools/llvm-mca/Dispatch.cpp
+++ b/llvm/tools/llvm-mca/Dispatch.cpp
@@ -119,17 +119,6 @@
       RegisterMappings[*I].first = nullptr;
 }
 
-// Update the number of used mappings in the event of instruction retired.
-// This mehod delegates to the register file the task of invalidating
-// register mappings that were created for instruction IS.
-void DispatchUnit::invalidateRegisterMappings(const Instruction &IS) {
-  for (const std::unique_ptr<WriteState> &WS : IS.getDefs()) {
-    DEBUG(dbgs() << "[RAT] Invalidating mapping for: ");
-    DEBUG(WS->dump());
-    RAT->invalidateRegisterMapping(*WS.get());
-  }
-}
-
 void RegisterFile::collectWrites(SmallVectorImpl<WriteState *> &Writes,
                                  unsigned RegID) const {
   assert(RegID && RegID < RegisterMappings.size());
@@ -243,7 +232,9 @@
       HWInstructionEvent(HWInstructionEvent::Retired, Index));
 
   const Instruction &IS = Owner->getInstruction(Index);
-  invalidateRegisterMappings(IS);
+  for (const std::unique_ptr<WriteState> &WS : IS.getDefs())
+    RAT->invalidateRegisterMapping(*WS.get());
+
   Owner->eraseInstruction(Index);
 }
 
@@ -374,7 +365,7 @@
 
   // Allocate new mappings.
   for (std::unique_ptr<WriteState> &WS : NewInst->getDefs())
-    addNewRegisterMapping(*WS);
+    RAT->addRegisterMapping(*WS);
 
   // Set the cycles left before the write-back stage.
   const InstrDesc &D = NewInst->getDesc();