Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html
In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.
llvm-svn: 323922
diff --git a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
index 279917a..5f4bb4b 100644
--- a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
+++ b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
@@ -4,7 +4,7 @@
define void @vst(i8* %m, [4 x i64] %v) {
entry:
; CHECK: vst:
-; CHECK: VST1d64Q killed %r{{[0-9]+}}, 8, %d{{[0-9]+}}, 14, %noreg, implicit killed %q{{[0-9]+}}_q{{[0-9]+}}
+; CHECK: VST1d64Q killed $r{{[0-9]+}}, 8, $d{{[0-9]+}}, 14, $noreg, implicit killed $q{{[0-9]+}}_q{{[0-9]+}}
%v0 = extractvalue [4 x i64] %v, 0
%v1 = extractvalue [4 x i64] %v, 1
@@ -37,7 +37,7 @@
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
; CHECK: vtbx4:
-; CHECK: VTBX4 {{.*}}, 14, %noreg, implicit %q{{[0-9]+}}_q{{[0-9]+}}
+; CHECK: VTBX4 {{.*}}, 14, $noreg, implicit $q{{[0-9]+}}_q{{[0-9]+}}
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
diff --git a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
index 86d09ce..d9a02de 100644
--- a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
+++ b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
@@ -81,24 +81,24 @@
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
- - { reg: '%r2' }
- - { reg: '%r3' }
-calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
- '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
- '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
- '%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
- '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
- '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
- '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
- '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
- '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
- '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
- '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
- '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
- '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
- '%d11_d12_d13_d14' ]
+ - { reg: '$r0' }
+ - { reg: '$r1' }
+ - { reg: '$r2' }
+ - { reg: '$r3' }
+calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
+ '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
+ '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
+ '$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
+ '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
+ '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
+ '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
+ '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
+ '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
+ '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
+ '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
+ '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
+ '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
+ '$d11_d12_d13_d14' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -114,46 +114,46 @@
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7', callee-saved-restored: true }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false }
+ - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7', callee-saved-restored: true }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2, %r3, %lr, %r7
+ liveins: $r0, $r1, $r2, $r3, $lr, $r7
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
- t2Bcc %bb.2.if.end, 2, killed %cpsr
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ t2CMPri $r3, 4, 14, $noreg, implicit-def $cpsr, debug-location !31
+ t2Bcc %bb.2.if.end, 2, killed $cpsr
bb.1:
- liveins: %lr, %r7
+ liveins: $lr, $r7
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- %r0 = t2MOVi -1, 14, %noreg, %noreg
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- tBX_RET 14, %noreg, implicit %r0, debug-location !34
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ $r0 = t2MOVi -1, 14, $noreg, $noreg
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ tBX_RET 14, $noreg, implicit $r0, debug-location !34
bb.2.if.end:
- liveins: %r0, %r2, %r3, %r7, %lr
+ liveins: $r0, $r2, $r3, $r7, $lr
- %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
+ $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8
- frame-setup CFI_INSTRUCTION offset %lr, -4
- frame-setup CFI_INSTRUCTION offset %r7, -8
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- %r1 = COPY killed %r2, debug-location !32
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- %r2 = COPY killed %r3, debug-location !32
- tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
- %r0 = t2MOVi 0, 14, %noreg, %noreg
- %sp = t2LDMIA_UPD %sp, 14, %noreg, def %r7, def %lr
- tBX_RET 14, %noreg, implicit %r0, debug-location !34
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ $r1 = COPY killed $r2, debug-location !32
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ $r2 = COPY killed $r3, debug-location !32
+ tBL 14, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !32
+ $r0 = t2MOVi 0, 14, $noreg, $noreg
+ $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr
+ tBX_RET 14, $noreg, implicit $r0, debug-location !34
# Verify that the DBG_VALUE is ignored.
-# CHECK: %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
+# CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
index ec6ea63..d667f17 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
@@ -4,14 +4,14 @@
define arm_aapcscc void @test_indirect_call(void() *%fptr) {
; CHECK-LABEL: name: test_indirect_call
-; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0
-; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
-; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY $r0
+; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0
+; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp
+; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp
+; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
entry:
notail call arm_aapcscc void %fptr()
ret void
@@ -21,9 +21,9 @@
define arm_aapcscc void @test_direct_call() {
; CHECK-LABEL: name: test_direct_call
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
entry:
notail call arm_aapcscc void @call_target()
ret void
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
index c8ed142..0c423b0 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
@@ -64,23 +64,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_eq_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ne_s32
@@ -94,23 +94,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ne_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ne), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ugt_s32
@@ -124,23 +124,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ugt_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_uge_s32
@@ -154,23 +154,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_uge_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ult_s32
@@ -184,23 +184,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ult_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ule_s32
@@ -214,23 +214,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ule_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sgt_s32
@@ -244,23 +244,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sgt_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sge_s32
@@ -274,23 +274,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sge_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_slt_s32
@@ -304,23 +304,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_slt_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(slt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sle_s32
@@ -334,23 +334,23 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sle_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sle), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_true_s32
@@ -364,19 +364,19 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_true_s32
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_false_s32
@@ -390,19 +390,19 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_false_s32
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oeq_s32
@@ -416,24 +416,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_oeq_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s32
@@ -447,24 +447,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ogt_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s32
@@ -478,24 +478,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_oge_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s32
@@ -509,24 +509,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_olt_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s32
@@ -540,24 +540,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ole_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s32
@@ -571,24 +571,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ord_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s32
@@ -602,24 +602,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ugt_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s32
@@ -633,24 +633,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_uge_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s32
@@ -664,24 +664,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ult_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s32
@@ -695,24 +695,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ule_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s32
@@ -726,24 +726,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_une_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(une), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s32
@@ -757,24 +757,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_uno_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s32
@@ -788,27 +788,27 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_one_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s32
@@ -822,27 +822,27 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ueq_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_true_s64
@@ -856,19 +856,19 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_true_s64
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(true), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_false_s64
@@ -882,19 +882,19 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_false_s64
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(false), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oeq_s64
@@ -908,24 +908,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_oeq_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s64
@@ -939,24 +939,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ogt_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s64
@@ -970,24 +970,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_oge_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(oge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s64
@@ -1001,24 +1001,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_olt_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(olt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s64
@@ -1032,24 +1032,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ole_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ole), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s64
@@ -1063,24 +1063,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ord_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ord), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s64
@@ -1094,24 +1094,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ugt_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s64
@@ -1125,24 +1125,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_uge_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(uge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s64
@@ -1156,24 +1156,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ult_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ult), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s64
@@ -1187,24 +1187,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ule_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ule), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s64
@@ -1218,24 +1218,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_une_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(une), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s64
@@ -1249,24 +1249,24 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_uno_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(uno), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s64
@@ -1280,27 +1280,27 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_one_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(one), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s64
@@ -1314,25 +1314,25 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ueq_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
index 3227febb..9cd5f45 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
@@ -63,24 +63,24 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mla_commutative
@@ -97,24 +97,24 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %2, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mla_v5
@@ -131,24 +131,24 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mls
@@ -165,24 +165,24 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_no_mls
@@ -199,25 +199,25 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3
- ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, %noreg, %noreg
+ ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_to_revsh
@@ -239,10 +239,10 @@
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 24
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -259,11 +259,11 @@
%9(s32) = G_OR %4(s32), %8(s32)
; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
- %r0 = COPY %9(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %9(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_to_revsh_commutative
@@ -285,10 +285,10 @@
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 24
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -305,11 +305,11 @@
%9(s32) = G_OR %8(s32), %4(s32)
; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
- %r0 = COPY %9(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %9(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_no_revsh_features
@@ -331,9 +331,9 @@
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 24
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -351,9 +351,9 @@
; We don't really care how this is folded as long as it's not into a REVSH.
; CHECK-NOT: REVSH
- %r0 = COPY %9(s32)
+ $r0 = COPY %9(s32)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_no_revsh_constants
@@ -375,9 +375,9 @@
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -395,9 +395,9 @@
; We don't really care how this is folded as long as it's not into a REVSH.
; CHECK-NOT: REVSH
- %r0 = COPY %9(s32)
+ $r0 = COPY %9(s32)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicrr
@@ -414,23 +414,23 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicrr_commutative
@@ -447,23 +447,23 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri
@@ -480,10 +480,10 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; This test and the following ones are a bit contrived, since they use a
; G_XOR that can be constant-folded. They exist mostly to validate the
@@ -495,13 +495,13 @@
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri_commutative_xor
@@ -518,23 +518,23 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1
%4(s32) = G_AND %0, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri_commutative_and
@@ -551,23 +551,23 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri_commutative_both
@@ -584,23 +584,23 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1
%4(s32) = G_AND %3, %0
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt
@@ -621,12 +621,12 @@
- { id: 8, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -637,13 +637,13 @@
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg
- %r0 = COPY %8(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %8(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt_commutative
@@ -664,12 +664,12 @@
- { id: 8, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -680,13 +680,13 @@
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %7, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg
- %r0 = COPY %8(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %8(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt_imm16_31
@@ -705,12 +705,12 @@
- { id: 6, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -719,13 +719,13 @@
%5(s32) = G_SHL %1, %4
%6(s32) = G_OR %3, %5
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, $noreg
- %r0 = COPY %6(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %6(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt_unshifted
@@ -744,12 +744,12 @@
- { id: 6, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -758,13 +758,13 @@
%5(s32) = G_AND %1, %4
%6(s32) = G_OR %3, %5
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, $noreg
- %r0 = COPY %6(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %6(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhtb_imm16
@@ -783,12 +783,12 @@
- { id: 6, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%3(s32) = G_AND %0, %2
@@ -797,13 +797,13 @@
%5(s32) = G_LSHR %1, %4
%6(s32) = G_OR %3, %5
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, $noreg
- %r0 = COPY %6(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %6(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhtb_imm1_15
@@ -824,12 +824,12 @@
- { id: 8, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%3(s32) = G_AND %0, %2
@@ -840,13 +840,13 @@
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, $noreg
- %r0 = COPY %8(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %8(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_movti16_0xffff
@@ -861,21 +861,21 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%2(s32) = G_OR %0, %1
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_vnmuls
@@ -891,22 +891,22 @@
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1
%3(s32) = G_FNEG %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %3(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %3(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vnmuls_reassociate
@@ -922,22 +922,22 @@
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FNEG %0
%3(s32) = G_FMUL %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %3(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %3(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vnmuld
@@ -953,22 +953,22 @@
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1
%3(s64) = G_FNEG %2
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %3(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %3(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_vfnmas
@@ -985,24 +985,24 @@
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2
%4(s32) = G_FNEG %3
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %4(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %4(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vfnmad
@@ -1020,25 +1020,25 @@
- { id: 5, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = COPY %d2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY %d2
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ %2(s64) = COPY $d2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FNEG %0
%4(s64) = G_FNEG %2
%5(s64) = G_FMA %3, %1, %4
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFNMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFNMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %5(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %5(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_vfmss
@@ -1055,24 +1055,24 @@
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FNEG %0
%4(s32) = G_FMA %3, %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %4(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %4(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vfmsd
@@ -1089,24 +1089,24 @@
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = COPY %d2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY %d2
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ %2(s64) = COPY $d2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FNEG %1
%4(s64) = G_FMA %0, %3, %2
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMSD [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMSD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %4(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %4(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_vfnmss
@@ -1123,22 +1123,22 @@
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FNEG %2
%4(s32) = G_FMA %0, %1, %3
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %4(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %4(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index db7cb7a..ffc9ed0 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -101,21 +101,21 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s1)
- ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_sext_s1
@@ -130,22 +130,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s32) = G_SEXT %1(s1)
- ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg
- ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg
+ ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_sext_s8
@@ -160,22 +160,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_SEXT %1(s8)
- ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, %noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_zext_s16
@@ -190,22 +190,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_ZEXT %1(s16)
- ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, %noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_anyext_s8
@@ -220,20 +220,20 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8)
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREG]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREG]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_anyext_s16
@@ -248,20 +248,20 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16)
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREG]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREG]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_s64
@@ -276,22 +276,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %d0
+ liveins: $r0, $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY $d0
- %2(p0) = COPY %r0
- ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+ %2(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_TRUNC %0(s64)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
G_STORE %1(s32), %2 :: (store 4)
- ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, %noreg
+ ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, $noreg
- BX_RET 14, %noreg
- ; CHECK: BX_RET 14, %noreg
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
...
---
name: test_add_s32
@@ -306,22 +306,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_fold_imm_s32
@@ -336,20 +336,20 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 255
%2(s32) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, %noreg, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_no_fold_imm_s32
@@ -364,22 +364,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 65535
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, %noreg
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, $noreg
%2(s32) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fadd_s32
@@ -394,22 +394,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fadd_s64
@@ -424,22 +424,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fsub_s32
@@ -454,22 +454,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FSUB %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fsub_s64
@@ -484,22 +484,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FSUB %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fmul_s32
@@ -514,22 +514,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fmul_s64
@@ -544,22 +544,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fdiv_s32
@@ -574,22 +574,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FDIV %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fdiv_s64
@@ -604,22 +604,22 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FDIV %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fneg_s32
@@ -633,19 +633,19 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FNEG %0
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fneg_s64
@@ -660,19 +660,19 @@
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = G_FNEG %0
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fma_s32
@@ -688,25 +688,25 @@
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
- %2(s32) = COPY %s2
- ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %2(s32) = COPY $s2
+ ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %3(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %3(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fma_s64
@@ -722,25 +722,25 @@
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
- %2(s64) = COPY %d2
- ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY %d2
+ %2(s64) = COPY $d2
+ ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FMA %0, %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %3(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %3(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fpext_s32_to_s64
@@ -754,19 +754,19 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s64) = G_FPEXT %0(s32)
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fptrunc_s64_to_s32
@@ -780,19 +780,19 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTRUNC %0(s64)
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fptosi_s32
@@ -806,20 +806,20 @@
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOSI %0(s32)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptosi_s64
@@ -833,20 +833,20 @@
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOSI %0(s64)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s32
@@ -860,20 +860,20 @@
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOUI %0(s32)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s64
@@ -887,20 +887,20 @@
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOUI %0(s64)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_s32
@@ -914,20 +914,20 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_sitofp_s64
@@ -941,20 +941,20 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_uitofp_s32
@@ -968,20 +968,20 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_uitofp_s64
@@ -995,20 +995,20 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_sub_s32
@@ -1023,22 +1023,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SUB %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_imm_s32
@@ -1053,20 +1053,20 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_rev_imm_s32
@@ -1081,20 +1081,20 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %1, %0
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s32
@@ -1109,22 +1109,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_MUL %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mulv5_s32
@@ -1139,22 +1139,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_MUL %0, %1
- ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sdiv_s32
@@ -1169,22 +1169,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SDIV %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_s32
@@ -1199,22 +1199,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_UDIV %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_lshr_s32
@@ -1229,22 +1229,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_LSHR %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_ashr_s32
@@ -1259,22 +1259,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_ASHR %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shl_s32
@@ -1289,22 +1289,22 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SHL %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_load_from_stack
@@ -1327,31 +1327,31 @@
# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
%0(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, %noreg, %noreg
+ ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4)
- ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, %noreg
+ ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, $noreg
- %r0 = COPY %1
- ; CHECK: %r0 = COPY [[LD32VREG]]
+ $r0 = COPY %1
+ ; CHECK: $r0 = COPY [[LD32VREG]]
%2(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, %noreg, %noreg
+ ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
%3(s1) = G_LOAD %2(p0) :: (load 1)
- ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, %noreg
+ ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, $noreg
%4(s32) = G_ANYEXT %3(s1)
; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
- %r0 = COPY %4
- ; CHECK: %r0 = COPY [[RES]]
+ $r0 = COPY %4
+ ; CHECK: $r0 = COPY [[RES]]
- BX_RET 14, %noreg
- ; CHECK: BX_RET 14, %noreg
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
...
---
name: test_load_f32
@@ -1365,19 +1365,19 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
- ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load 4)
- ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, %noreg
+ ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, $noreg
- %s0 = COPY %1
- ; CHECK: %s0 = COPY %[[V]]
+ $s0 = COPY %1
+ ; CHECK: $s0 = COPY %[[V]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_load_f64
@@ -1391,19 +1391,19 @@
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
- ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8)
- ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, %noreg
+ ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, $noreg
- %d0 = COPY %1
- ; CHECK: %d0 = COPY %[[V]]
+ $d0 = COPY %1
+ ; CHECK: $d0 = COPY %[[V]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_stores
@@ -1427,31 +1427,31 @@
# CHECK: id: [[F64:[0-9]+]], class: dpr
body: |
bb.0:
- liveins: %r0, %r1, %s0, %d0
+ liveins: $r0, $r1, $s0, $d0
- %0(p0) = COPY %r0
- %3(s32) = COPY %r1
- %4(s32) = COPY %s0
- %5(s64) = COPY %d2
+ %0(p0) = COPY $r0
+ %3(s32) = COPY $r1
+ %4(s32) = COPY $s0
+ %5(s64) = COPY $d2
%1(s8) = G_TRUNC %3(s32)
%2(s16) = G_TRUNC %3(s32)
G_STORE %1(s8), %0(p0) :: (store 1)
- ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg
+ ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, $noreg
G_STORE %2(s16), %0(p0) :: (store 2)
- ; CHECK: STRH %[[I32]], %[[P]], %noreg, 0, 14, %noreg
+ ; CHECK: STRH %[[I32]], %[[P]], $noreg, 0, 14, $noreg
G_STORE %3(s32), %0(p0) :: (store 4)
- ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg
+ ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, $noreg
G_STORE %4(s32), %0(p0) :: (store 4)
- ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, %noreg
+ ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, $noreg
G_STORE %5(s64), %0(p0) :: (store 8)
- ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, %noreg
+ ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, $noreg
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_gep
@@ -1466,19 +1466,19 @@
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
- ; CHECK: %[[PTR:[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: %[[PTR:[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY $r1
%2(p0) = G_GEP %0, %1(s32)
- ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, %noreg, %noreg
+ ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, $noreg, $noreg
- %r0 = COPY %2(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constant_imm
@@ -1492,10 +1492,10 @@
body: |
bb.0:
%0(s32) = G_CONSTANT 42
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constant_cimm
@@ -1511,10 +1511,10 @@
; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
; We still want to see the same thing in the output though.
%0(s32) = G_CONSTANT i32 42
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_pointer_constant_unconstrained
@@ -1528,11 +1528,11 @@
body: |
bb.0:
%0(p0) = G_CONSTANT i32 0
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
; This leaves %0 unconstrained before the G_CONSTANT is selected.
- %r0 = COPY %0(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_pointer_constant_constrained
@@ -1546,7 +1546,7 @@
body: |
bb.0:
%0(p0) = G_CONSTANT i32 0
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
; This constrains %0 before the G_CONSTANT is selected.
G_STORE %0(p0), %0(p0) :: (store 4)
@@ -1563,16 +1563,16 @@
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32)
- ; CHECK: [[INT:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[INT:%[0-9]+]]:gpr = COPY $r0
- %r0 = COPY %1(p0)
- ; CHECK: %r0 = COPY [[INT]]
+ $r0 = COPY %1(p0)
+ ; CHECK: $r0 = COPY [[INT]]
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_ptrtoint_s32
@@ -1586,16 +1586,16 @@
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0)
- ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[PTR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[PTR]]
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_s32
@@ -1611,25 +1611,25 @@
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s32) = G_SELECT %2(s1), %0, %1
- ; CHECK: CMPri [[VREGY]], 0, 14, %noreg, implicit-def %cpsr
- ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
+ ; CHECK: CMPri [[VREGY]], 0, 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RES]]
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[RES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_ptr
@@ -1646,28 +1646,28 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(p0) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(p0) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(p0) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY %r2
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY $r2
%3(s1) = G_TRUNC %2(s32)
%4(p0) = G_SELECT %3(s1), %0, %1
- ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr
- ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
+ ; CHECK: CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
- %r0 = COPY %4(p0)
- ; CHECK: %r0 = COPY [[RES]]
+ $r0 = COPY %4(p0)
+ ; CHECK: $r0 = COPY [[RES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_br
@@ -1683,15 +1683,15 @@
bb.0:
; CHECK: bb.0
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32)
G_BRCOND %1(s1), %bb.1
- ; CHECK: TSTri [[COND32]], 1, 14, %noreg, implicit-def %cpsr
- ; CHECK: Bcc %bb.1, 1, %cpsr
+ ; CHECK: TSTri [[COND32]], 1, 14, $noreg, implicit-def $cpsr
+ ; CHECK: Bcc %bb.1, 1, $cpsr
G_BR %bb.2
; CHECK: B %bb.2
@@ -1705,8 +1705,8 @@
bb.2:
; CHECK: bb.2
- BX_RET 14, %noreg
- ; CHECK: BX_RET 14, %noreg
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
...
---
name: test_phi_s32
@@ -1726,15 +1726,15 @@
bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
- %3(s32) = COPY %r2
- ; CHECK: [[V1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[V2:%[0-9]+]]:gpr = COPY %r2
+ %2(s32) = COPY $r1
+ %3(s32) = COPY $r2
+ ; CHECK: [[V1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[V2:%[0-9]+]]:gpr = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1751,8 +1751,8 @@
%4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
; CHECK: {{%[0-9]+}}:gpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_s64
@@ -1772,15 +1772,15 @@
bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %d0, %d1
+ liveins: $r0, $d0, $d1
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s64) = COPY %d0
- %3(s64) = COPY %d1
- ; CHECK: [[V1:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[V2:%[0-9]+]]:dpr = COPY %d1
+ %2(s64) = COPY $d0
+ %3(s64) = COPY $d1
+ ; CHECK: [[V1:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[V2:%[0-9]+]]:dpr = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1797,8 +1797,8 @@
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
- %d0 = COPY %4(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %4(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_soft_fp_double
@@ -1815,13 +1815,13 @@
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r2
- ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY %r2
+ %0(s32) = COPY $r2
+ ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2
- %1(s32) = COPY %r3
- ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY %r3
+ %1(s32) = COPY $r3
+ ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]]
@@ -1829,12 +1829,12 @@
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]
- %r0 = COPY %3
- ; CHECK: %r0 = COPY [[OUT1]]
+ $r0 = COPY %3
+ ; CHECK: $r0 = COPY [[OUT1]]
- %r1 = COPY %4
- ; CHECK: %r1 = COPY [[OUT2]]
+ $r1 = COPY %4
+ ; CHECK: $r1 = COPY [[OUT2]]
- BX_RET 14, %noreg, implicit %r0, implicit %r1
- ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
+ ; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
index 9c070e8..95d2c30 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -4,22 +4,22 @@
define void @test_void_return() {
; CHECK-LABEL: name: test_void_return
-; CHECK: BX_RET 14, %noreg
+; CHECK: BX_RET 14, $noreg
entry:
ret void
}
define signext i1 @test_add_i1(i1 %x, i1 %y) {
; CHECK-LABEL: name: test_add_i1
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
-; CHECK: %r0 = COPY [[EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i1 %x, %y
ret i1 %sum
@@ -27,15 +27,15 @@
define i8 @test_add_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_add_i8
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i8 %x, %y
ret i8 %sum
@@ -43,15 +43,15 @@
define i8 @test_sub_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_sub_i8
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
-; CHECK: %r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RES_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%res = sub i8 %x, %y
ret i8 %res
@@ -59,27 +59,27 @@
define signext i8 @test_return_sext_i8(i8 %x) {
; CHECK-LABEL: name: test_return_sext_i8
-; CHECK: liveins: %r0
-; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
-; CHECK: %r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGEXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
ret i8 %x
}
define i16 @test_add_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_add_i16
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i16 %x, %y
ret i16 %sum
@@ -87,15 +87,15 @@
define i16 @test_sub_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_sub_i16
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
-; CHECK: %r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RES_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%res = sub i16 %x, %y
ret i16 %res
@@ -103,24 +103,24 @@
define zeroext i16 @test_return_zext_i16(i16 %x) {
; CHECK-LABEL: name: test_return_zext_i16
-; CHECK: liveins: %r0
-; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
-; CHECK: %r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGEXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
ret i16 %x
}
define i32 @test_add_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_add_i32
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: %r0 = COPY [[SUM]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i32 %x, %y
ret i32 %sum
@@ -128,12 +128,12 @@
define i32 @test_sub_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_sub_i32
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
-; CHECK: %r0 = COPY [[RES]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RES]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%res = sub i32 %x, %y
ret i32 %res
@@ -144,13 +144,13 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
-; CHECK: %r0 = COPY [[SUM]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i32 %p2, %p5
ret i32 %sum
@@ -162,16 +162,16 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i16 %p1, %p5
ret i16 %sum
@@ -183,16 +183,16 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load 4
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
@@ -204,15 +204,15 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_LOAD [[FIP4]](p0){{.*}}load 1
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
@@ -224,21 +224,21 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]]
; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
-; CHECK: %r0 = COPY [[VREGP5ZEXT]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGP5ZEXT]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
ret i16 %p5
}
define i16 @test_ptr_arg(i16* %p) {
; CHECK-LABEL: name: test_ptr_arg
-; CHECK: liveins: %r0
-; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load 2
entry:
%v = load i16, i16* %p
@@ -248,11 +248,11 @@
define i32* @test_ptr_ret(i32** %p) {
; Test pointer returns and pointer-to-pointer arguments
; CHECK-LABEL: name: test_ptr_ret
-; CHECK: liveins: %r0
-; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
-; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%v = load i32*, i32** %p
ret i32* %v
@@ -262,12 +262,12 @@
; CHECK-LABEL: name: test_ptr_arg_on_stack
; CHECK: fixedStack:
; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]]
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
-; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%v = load i32, i32* %p
ret i32 %v
@@ -279,13 +279,13 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
-; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%v = fadd float %p1, %p5
ret float %v
@@ -308,13 +308,13 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: %s0, %s1, %s2, %s3, %s4, %s5, %s6, %s7, %s8, %s9, %s10, %s11, %s12, %s13, %s14, %s15
-; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: liveins: $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $s8, $s9, $s10, $s11, $s12, $s13, $s14, $s15
+; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $s1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: %s0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %s0
+; CHECK: $s0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $s0
entry:
%v = fadd float %p1, %q1
ret float %v
@@ -329,13 +329,13 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
-; CHECK: liveins: %d0, %d1, %d2, %d3, %d4, %d5, %d6, %d7
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d1
+; CHECK: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: %d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %d0
+; CHECK: $d0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $d0
entry:
%v = fadd double %p1, %q1
ret double %v
@@ -349,9 +349,9 @@
; CHECK-DAG: id: [[P3:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 16{{.*}}size: 8
; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 24{{.*}}size: 8
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[VREGP1LO:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[VREGP1HI:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK-DAG: [[VREGP1LO:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[VREGP1HI:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1LO]](s32), [[VREGP1HI]](s32)
; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
@@ -359,9 +359,9 @@
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: %r0 = COPY [[VREGVLO]]
-; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK-DAG: $r0 = COPY [[VREGVLO]]
+; CHECK-DAG: $r1 = COPY [[VREGVHI]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p1, %p5
ret double %v
@@ -377,13 +377,13 @@
; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
-; CHECK: liveins: %d0, %d2, %d3, %d4, %d5, %d6, %d7, %s2
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d2
+; CHECK: liveins: $d0, $d2, $d3, $d4, $d5, $d6, $d7, $s2
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d2
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: %d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %d0
+; CHECK: $d0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $d0
entry:
%v = fadd double %p1, %q1
ret double %v
@@ -394,9 +394,9 @@
; CHECK-LABEL: name: test_double_gap_aapcscc
; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK: liveins: %r0, %r2, %r3
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r2, $r3
+; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
@@ -404,9 +404,9 @@
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: %r0 = COPY [[VREGVLO]]
-; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK-DAG: $r0 = COPY [[VREGVLO]]
+; CHECK-DAG: $r1 = COPY [[VREGVHI]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p0, %p1
ret double %v
@@ -417,9 +417,9 @@
; CHECK-LABEL: name: test_double_gap2_aapcscc
; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK: liveins: %r0, %r1, %r2
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2
+; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
@@ -427,9 +427,9 @@
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: %r0 = COPY [[VREGVLO]]
-; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK-DAG: $r0 = COPY [[VREGVLO]]
+; CHECK-DAG: $r1 = COPY [[VREGVHI]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p0, %p1
ret double %v
@@ -437,7 +437,7 @@
define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
@@ -451,8 +451,8 @@
define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -471,8 +471,8 @@
define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -490,10 +490,10 @@
define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[ARG4:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: [[ARG4:%[0-9]+]]:_(s32) = COPY $r3
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
index 941b7aa..7663be7 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
@@ -35,27 +35,27 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
%2(s32) = G_SDIV %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_i32
@@ -71,27 +71,27 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
%2(s32) = G_UDIV %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sdiv_i16
@@ -110,10 +110,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -124,28 +124,28 @@
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV
%4(s16) = G_SDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_i16
@@ -164,10 +164,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
@@ -176,28 +176,28 @@
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV
%4(s16) = G_UDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sdiv_i8
@@ -216,10 +216,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
@@ -230,28 +230,28 @@
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV
%4(s8) = G_SDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_i8
@@ -270,10 +270,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -282,28 +282,28 @@
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV
%4(s8) = G_UDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_srem_i32
@@ -319,29 +319,29 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
%2(s32) = G_SREM %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_urem_i32
@@ -357,29 +357,29 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
%2(s32) = G_UREM %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_srem_i16
@@ -398,10 +398,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -412,30 +412,30 @@
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM
%4(s16) = G_SREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_urem_i16
@@ -454,10 +454,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
@@ -466,30 +466,30 @@
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM
%4(s16) = G_UREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_srem_i8
@@ -508,10 +508,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
@@ -522,30 +522,30 @@
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM
%4(s8) = G_SREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_urem_i8
@@ -564,10 +564,10 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -576,28 +576,28 @@
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM
%4(s8) = G_UREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index f381076..30e065a 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -91,28 +91,28 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; CHECK-NOT: G_FREM
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; HARD-DAG: %s0 = COPY [[X]]
- ; HARD-DAG: %s1 = COPY [[Y]]
- ; SOFT: BL &fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; HARD: BL &fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; HARD-DAG: $s0 = COPY [[X]]
+ ; HARD-DAG: $s1 = COPY [[Y]]
+ ; SOFT: BL &fmodf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; HARD: BL &fmodf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM
%2(s32) = G_FREM %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_frem_double
@@ -134,7 +134,7 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
; The inputs may be in the wrong order (depending on the target's
; endianness), but that's orthogonal to what we're trying to test here.
@@ -142,35 +142,35 @@
; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod.
; For hard float, the values need to end up in D0 and D1.
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
; CHECK-NOT: G_FREM
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; HARD-DAG: %d0 = COPY [[X]]
- ; HARD-DAG: %d1 = COPY [[Y]]
- ; SOFT: BL &fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; HARD: BL &fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; HARD-DAG: $d0 = COPY [[X]]
+ ; HARD-DAG: $d1 = COPY [[Y]]
+ ; SOFT: BL &fmod, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; HARD: BL &fmod, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM
%6(s64) = G_FREM %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fpow_float
@@ -186,28 +186,28 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; CHECK-NOT: G_FPOW
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; HARD-DAG: %s0 = COPY [[X]]
- ; HARD-DAG: %s1 = COPY [[Y]]
- ; SOFT: BL &powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; HARD: BL &powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; HARD-DAG: $s0 = COPY [[X]]
+ ; HARD-DAG: $s1 = COPY [[Y]]
+ ; SOFT: BL &powf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; HARD: BL &powf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW
%2(s32) = G_FPOW %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fpow_double
@@ -229,7 +229,7 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
; The inputs may be in the wrong order (depending on the target's
; endianness), but that's orthogonal to what we're trying to test here.
@@ -237,35 +237,35 @@
; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow.
; For hard float, the values need to end up in D0 and D1.
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
; CHECK-NOT: G_FPOW
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; HARD-DAG: %d0 = COPY [[X]]
- ; HARD-DAG: %d1 = COPY [[Y]]
- ; SOFT: BL &pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; HARD: BL &pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; HARD-DAG: $d0 = COPY [[X]]
+ ; HARD-DAG: $d1 = COPY [[Y]]
+ ; SOFT: BL &pow, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; HARD: BL &pow, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW
%6(s64) = G_FPOW %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fadd_float
@@ -281,26 +281,26 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FADD [[X]], [[Y]]
; SOFT-NOT: G_FADD
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fadd, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__addsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
%2(s32) = G_FADD %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fadd_double
@@ -322,16 +322,16 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -339,20 +339,20 @@
; HARD: [[R:%[0-9]+]]:_(s64) = G_FADD [[X]], [[Y]]
; SOFT-NOT: G_FADD
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dadd, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__adddf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
%6(s64) = G_FADD %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fsub_float
@@ -368,26 +368,26 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]]
; SOFT-NOT: G_FSUB
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
%2(s32) = G_FSUB %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fsub_double
@@ -409,16 +409,16 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -426,20 +426,20 @@
; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]]
; SOFT-NOT: G_FSUB
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
%6(s64) = G_FSUB %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fmul_float
@@ -455,26 +455,26 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FMUL [[X]], [[Y]]
; SOFT-NOT: G_FMUL
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fmul, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__mulsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fmul, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__mulsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
%2(s32) = G_FMUL %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fmul_double
@@ -496,16 +496,16 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -513,20 +513,20 @@
; HARD: [[R:%[0-9]+]]:_(s64) = G_FMUL [[X]], [[Y]]
; SOFT-NOT: G_FMUL
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dmul, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__muldf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dmul, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__muldf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
%6(s64) = G_FMUL %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fdiv_float
@@ -542,26 +542,26 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FDIV [[X]], [[Y]]
; SOFT-NOT: G_FDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fdiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__divsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fdiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__divsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
%2(s32) = G_FDIV %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fdiv_double
@@ -583,16 +583,16 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -600,20 +600,20 @@
; HARD: [[R:%[0-9]+]]:_(s64) = G_FDIV [[X]], [[Y]]
; SOFT-NOT: G_FDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_ddiv, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__divdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_ddiv, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__divdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
%6(s64) = G_FDIV %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fconstant_float
@@ -634,9 +634,9 @@
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1080033280
; SOFT-NOT: G_FCONSTANT
%0(s32) = G_FCONSTANT float -1.25
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fconstant_double
@@ -661,12 +661,12 @@
; SOFT-NOT: G_FCONSTANT
%0(s64) = G_FCONSTANT double -2.4
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
- ; SOFT-DAG: %r0 = COPY [[HI]]
- ; SOFT-DAG: %r1 = COPY [[LO]]
+ ; SOFT-DAG: $r0 = COPY [[HI]]
+ ; SOFT-DAG: $r1 = COPY [[LO]]
%1(s32),%2(s32) = G_UNMERGE_VALUES %0(s64)
- %r0 = COPY %2(s32)
- %r1 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %2(s32)
+ $r1 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fneg_float
@@ -681,25 +681,25 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_FNEG [[X]]
; SOFT-NOT: G_FNEG
; SOFT-DAG: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[ZERO]]
- ; SOFT-DAG: %r1 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[ZERO]]
+ ; SOFT-DAG: $r1 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FNEG
%1(s32) = G_FNEG %0
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fneg_double
@@ -718,12 +718,12 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s64) = G_FNEG [[X]]
@@ -731,20 +731,20 @@
; SOFT-DAG: [[NEGATIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SOFT-DAG: [[POSITIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[NEGATIVE_ZERO]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[POSITIVE_ZERO]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[NEGATIVE_ZERO]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[POSITIVE_ZERO]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FNEG
%3(s64) = G_FNEG %2
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%4(s32),%5(s32) = G_UNMERGE_VALUES %3(s64)
- %r0 = COPY %4(s32)
- %r1 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %4(s32)
+ $r1 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fpext_float_to_double
@@ -761,28 +761,28 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s64) = G_FPEXT [[X]]
; SOFT-NOT: G_FPEXT
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_f2d, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__extendsfdf2, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_f2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__extendsfdf2, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPEXT
%1(s64) = G_FPEXT %0(s32)
; HARD: G_UNMERGE_VALUES [[R]](s64)
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[R0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[R1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[R0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[R1]]
%2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- %r0 = COPY %2(s32)
- %r1 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %2(s32)
+ $r1 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fptrunc_double_to_float
@@ -799,28 +799,28 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTRUNC [[X]]
; SOFT-NOT: G_FPTRUNC
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_d2f, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__truncdfsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_d2f, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__truncdfsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTRUNC
%3(s32) = G_FPTRUNC %2(s64)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
---
---
name: test_fptosi_float
@@ -835,23 +835,23 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOSI [[X]]
; SOFT-NOT: G_FPTOSI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_f2iz, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixsfsi, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_f2iz, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixsfsi, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
%1(s32) = G_FPTOSI %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptosi_double
@@ -868,28 +868,28 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOSI [[X]]
; SOFT-NOT: G_FPTOSI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_d2iz, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixdfsi, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_d2iz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
%3(s32) = G_FPTOSI %2(s64)
- ; CHECK: %r0 = COPY [[R]](s32)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]](s32)
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_float
@@ -904,23 +904,23 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOUI [[X]]
; SOFT-NOT: G_FPTOUI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_f2uiz, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixunssfsi, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_f2uiz, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixunssfsi, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
%1(s32) = G_FPTOUI %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_double
@@ -937,28 +937,28 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOUI [[X]]
; SOFT-NOT: G_FPTOUI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_d2uiz, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixunsdfsi, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_d2uiz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixunsdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
%3(s32) = G_FPTOUI %2(s64)
- ; CHECK: %r0 = COPY [[R]](s32)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]](s32)
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_float
@@ -973,23 +973,23 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_SITOFP [[X]]
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_i2f, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__floatsisf, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_i2f, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__floatsisf, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SITOFP
%1(s32) = G_SITOFP %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_double
@@ -1006,28 +1006,28 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s64) = G_SITOFP [[X]]
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_i2d, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__floatsidf, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; SOFT: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_i2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__floatsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SITOFP
%1(s64) = G_SITOFP %0(s32)
; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]]
%2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- ; CHECK-DAG: %r0 = COPY [[R0]](s32)
- ; CHECK-DAG: %r1 = COPY [[R1]](s32)
- %r0 = COPY %2(s32)
- %r1 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ ; CHECK-DAG: $r0 = COPY [[R0]](s32)
+ ; CHECK-DAG: $r1 = COPY [[R1]](s32)
+ $r0 = COPY %2(s32)
+ $r1 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_uitofp_float
@@ -1042,23 +1042,23 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_UITOFP [[X]]
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_ui2f, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__floatunsisf, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_ui2f, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__floatunsisf, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UITOFP
%1(s32) = G_UITOFP %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_uitofp_double
@@ -1075,28 +1075,28 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s64) = G_UITOFP [[X]]
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_ui2d, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__floatunsidf, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; SOFT: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_ui2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__floatunsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UITOFP
%1(s64) = G_UITOFP %0(s32)
; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]]
%2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- ; CHECK-DAG: %r0 = COPY [[R0]](s32)
- ; CHECK-DAG: %r1 = COPY [[R1]](s32)
- %r0 = COPY %2(s32)
- %r1 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ ; CHECK-DAG: $r0 = COPY [[R0]](s32)
+ ; CHECK-DAG: $r1 = COPY [[R1]](s32)
+ $r0 = COPY %2(s32)
+ $r1 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
...
name: test_fcmp_true_s32
@@ -1113,16 +1113,16 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
- ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
@@ -1133,7 +1133,7 @@
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
- ; CHECK: %r0 = COPY [[REXT]]
+ ; CHECK: $r0 = COPY [[REXT]]
...
---
name: test_fcmp_false_s32
@@ -1150,16 +1150,16 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
- ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
@@ -1170,7 +1170,7 @@
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
- ; CHECK: %r0 = COPY [[REXT]]
+ ; CHECK: $r0 = COPY [[REXT]]
...
---
name: test_fcmp_oeq_s32
@@ -1187,22 +1187,22 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1214,9 +1214,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s32
@@ -1233,22 +1233,22 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1260,9 +1260,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s32
@@ -1279,22 +1279,22 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1306,9 +1306,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s32
@@ -1325,22 +1325,22 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1352,9 +1352,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s32
@@ -1371,22 +1371,22 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1398,9 +1398,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s32
@@ -1417,30 +1417,30 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s32
@@ -1457,21 +1457,21 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1479,9 +1479,9 @@
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s32
@@ -1498,21 +1498,21 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1520,9 +1520,9 @@
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s32
@@ -1539,21 +1539,21 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1561,9 +1561,9 @@
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s32
@@ -1580,21 +1580,21 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1602,9 +1602,9 @@
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s32
@@ -1621,21 +1621,21 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(une), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__nesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1643,9 +1643,9 @@
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s32
@@ -1662,22 +1662,22 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1689,9 +1689,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s32
@@ -1708,32 +1708,32 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
@@ -1749,9 +1749,9 @@
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s32
@@ -1768,32 +1768,32 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
@@ -1809,9 +1809,9 @@
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_true_s64
@@ -1832,16 +1832,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -1858,9 +1858,9 @@
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_false_s64
@@ -1881,16 +1881,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -1908,9 +1908,9 @@
; SOFT-NOT: G_FCMP
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oeq_s64
@@ -1931,16 +1931,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -1950,13 +1950,13 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1968,9 +1968,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s64
@@ -1991,16 +1991,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2010,13 +2010,13 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2028,9 +2028,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s64
@@ -2051,16 +2051,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2070,13 +2070,13 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2088,9 +2088,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s64
@@ -2111,16 +2111,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2130,13 +2130,13 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2148,9 +2148,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s64
@@ -2171,16 +2171,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2190,13 +2190,13 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2208,9 +2208,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s64
@@ -2231,16 +2231,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2249,22 +2249,22 @@
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s64
@@ -2285,16 +2285,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2303,13 +2303,13 @@
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2317,9 +2317,9 @@
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s64
@@ -2340,16 +2340,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2358,13 +2358,13 @@
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2372,9 +2372,9 @@
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s64
@@ -2395,16 +2395,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2413,13 +2413,13 @@
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2427,9 +2427,9 @@
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s64
@@ -2450,16 +2450,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2468,13 +2468,13 @@
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2482,9 +2482,9 @@
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s64
@@ -2505,16 +2505,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2523,13 +2523,13 @@
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__nedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2537,9 +2537,9 @@
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s64
@@ -2560,16 +2560,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2579,13 +2579,13 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2597,9 +2597,9 @@
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s64
@@ -2620,16 +2620,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2639,25 +2639,25 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
@@ -2673,9 +2673,9 @@
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s64
@@ -2696,16 +2696,16 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2715,25 +2715,25 @@
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
@@ -2749,7 +2749,7 @@
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
index 5fe0d86..914869c 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
@@ -21,33 +21,33 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Z:%[0-9]+]]:_(s32) = COPY %r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Z:%[0-9]+]]:_(s32) = COPY $r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
; HARD: [[R:%[0-9]+]]:_(s32) = G_FMA [[X]], [[Y]], [[Z]]
; SOFT-NOT: G_FMA
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-ABI-DAG: %r0 = COPY [[X]]
- ; SOFT-ABI-DAG: %r1 = COPY [[Y]]
- ; SOFT-ABI-DAG: %r2 = COPY [[Z]]
- ; SOFT-ABI: BL &fmaf, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit-def %r0
- ; SOFT-ABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD-ABI-DAG: %s0 = COPY [[X]]
- ; HARD-ABI-DAG: %s1 = COPY [[Y]]
- ; HARD-ABI-DAG: %s2 = COPY [[Z]]
- ; HARD-ABI: BL &fmaf, {{.*}}, implicit %s0, implicit %s1, implicit %s2, implicit-def %s0
- ; HARD-ABI: [[R:%[0-9]+]]:_(s32) = COPY %s0
+ ; SOFT-ABI-DAG: $r0 = COPY [[X]]
+ ; SOFT-ABI-DAG: $r1 = COPY [[Y]]
+ ; SOFT-ABI-DAG: $r2 = COPY [[Z]]
+ ; SOFT-ABI: BL &fmaf, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit-def $r0
+ ; SOFT-ABI: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD-ABI-DAG: $s0 = COPY [[X]]
+ ; HARD-ABI-DAG: $s1 = COPY [[Y]]
+ ; HARD-ABI-DAG: $s2 = COPY [[Z]]
+ ; HARD-ABI: BL &fmaf, {{.*}}, implicit $s0, implicit $s1, implicit $s2, implicit-def $s0
+ ; HARD-ABI: [[R:%[0-9]+]]:_(s32) = COPY $s0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMA
%3(s32) = G_FMA %0, %1, %2
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fma_double
@@ -69,16 +69,16 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
; HARD-ABI-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
@@ -88,34 +88,34 @@
; HARD: [[R:%[0-9]+]]:_(s64) = G_FMA [[X]], [[X]], [[Y]]
; SOFT-NOT: G_FMA
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-ABI-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-ABI-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-ABI-DAG: %r{{[2-3]}} = COPY [[X0]]
- ; SOFT-ABI-DAG: %r{{[2-3]}} = COPY [[X1]]
- ; SOFT-ABI: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+ ; SOFT-ABI-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-ABI-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-ABI-DAG: $r{{[2-3]}} = COPY [[X0]]
+ ; SOFT-ABI-DAG: $r{{[2-3]}} = COPY [[X1]]
+ ; SOFT-ABI: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; SOFT-ABI: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-ABI: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; SOFT-ABI: G_STORE [[Y0]](s32), [[FI1]](p0){{.*}}store 8 into stack
; SOFT-ABI: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; SOFT-ABI: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[FI1]], [[OFF2]](s32)
; SOFT-ABI: G_STORE [[Y1]](s32), [[FI2]](p0){{.*}}store 8 into stack
- ; SOFT-ABI: BL &fma, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
- ; HARD-ABI-DAG: %d0 = COPY [[X]]
- ; HARD-ABI-DAG: %d1 = COPY [[X]]
- ; HARD-ABI-DAG: %d2 = COPY [[Y]]
- ; HARD-ABI: BL &fma, {{.*}}, implicit %d0, implicit %d1, implicit %d2, implicit-def %d0
- ; HARD-ABI: [[R:%[0-9]+]]:_(s64) = COPY %d0
+ ; SOFT-ABI: BL &fma, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+ ; HARD-ABI-DAG: $d0 = COPY [[X]]
+ ; HARD-ABI-DAG: $d1 = COPY [[X]]
+ ; HARD-ABI-DAG: $d2 = COPY [[Y]]
+ ; HARD-ABI: BL &fma, {{.*}}, implicit $d0, implicit $d1, implicit $d2, implicit-def $d0
+ ; HARD-ABI: [[R:%[0-9]+]]:_(s64) = COPY $d0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMA
%6(s64) = G_FMA %4, %4, %5
; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
; HARD-ABI: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- ; CHECK-DAG: %r0 = COPY [[R0]]
- ; CHECK-DAG: %r1 = COPY [[R1]]
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ ; CHECK-DAG: $r0 = COPY [[R0]]
+ ; CHECK-DAG: $r1 = COPY [[R1]]
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index d88f48c..ad6bb49 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -74,15 +74,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0(p0) :: (load 1)
%2(s32) = G_SEXT %1
; G_SEXT with s8 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_zext_s16
@@ -98,15 +98,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(s32) = G_ZEXT %1
; G_ZEXT with s16 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_inttoptr_s32
@@ -121,14 +121,14 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32)
; G_INTTOPTR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_INTTOPTR {{%[0-9]+}}
- %r0 = COPY %1(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_ptrtoint_s32
@@ -143,14 +143,14 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0)
; G_PTRTOINT with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_PTRTOINT {{%[0-9]+}}
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s8
@@ -169,11 +169,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_ADD %1, %3
; G_ADD with s8 should widen
@@ -181,8 +181,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s16
@@ -201,11 +201,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_ADD %1, %3
; G_ADD with s16 should widen
@@ -213,8 +213,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s32
@@ -230,15 +230,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ADD %0, %1
; G_ADD with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -258,11 +258,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_SUB %1, %3
; G_SUB with s8 should widen
@@ -270,8 +270,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_s16
@@ -290,11 +290,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_SUB %1, %3
; G_SUB with s16 should widen
@@ -302,8 +302,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_s32
@@ -319,15 +319,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SUB %0, %1
; G_SUB with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -347,11 +347,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_MUL %1, %3
; G_MUL with s8 should widen
@@ -359,8 +359,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s16
@@ -379,11 +379,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_MUL %1, %3
; G_MUL with s16 should widen
@@ -391,8 +391,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s32
@@ -408,15 +408,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_MUL %0, %1
; G_MUL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -436,11 +436,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_AND %1, %3
; G_AND with s8 should widen
@@ -448,8 +448,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s16
@@ -468,11 +468,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_AND %1, %3
; G_AND with s16 should widen
@@ -480,8 +480,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s32
@@ -497,15 +497,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_AND %0, %1
; G_AND with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -525,11 +525,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_OR %1, %3
; G_OR with s8 should widen
@@ -537,8 +537,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_or_s16
@@ -557,11 +557,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_OR %1, %3
; G_OR with s16 should widen
@@ -569,8 +569,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_or_s32
@@ -586,15 +586,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_OR %0, %1
; G_OR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -614,11 +614,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_XOR %1, %3
; G_XOR with s8 should widen
@@ -626,8 +626,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_xor_s16
@@ -646,11 +646,11 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_XOR %1, %3
; G_XOR with s16 should widen
@@ -658,8 +658,8 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_xor_s32
@@ -675,15 +675,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_XOR %0, %1
; G_XOR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -700,15 +700,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_LSHR %0, %1
; G_LSHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -725,15 +725,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ASHR %0, %1
; G_ASHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -750,15 +750,15 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SHL %0, %1
; G_SHL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -781,15 +781,15 @@
# CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
; This is legal, so we should find it unchanged in the output
; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
%0(p0) = G_FRAME_INDEX %fixed-stack.2
%1(s32) = G_LOAD %0(p0) :: (load 4)
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_legal_loads_stores
@@ -809,7 +809,7 @@
- { id: 6, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
; These are all legal, so we should find them unchanged in the output
; CHECK-DAG: G_STORE {{%[0-9]+}}(s64), %0(p0)
@@ -824,7 +824,7 @@
; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0(p0)
; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0(p0)
; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0(p0)
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8)
G_STORE %1(s64), %0(p0) :: (store 8)
%2(s32) = G_LOAD %0(p0) :: (load 4)
@@ -837,7 +837,7 @@
G_STORE %5(s1), %0(p0) :: (store 1)
%6(p0) = G_LOAD %0(p0) :: (load 4)
G_STORE %6(p0), %0(p0) :: (store 4)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_gep
@@ -853,16 +853,16 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
- %1(s32) = COPY %r1
+ %0(p0) = COPY $r0
+ %1(s32) = COPY $r1
; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
%2(p0) = G_GEP %0, %1(s32)
- %r0 = COPY %2(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constants
@@ -884,9 +884,9 @@
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %4(p0) = COPY %r0
+ %4(p0) = COPY $r0
%0(s32) = G_CONSTANT 42
; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42
@@ -924,8 +924,8 @@
; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 16
; CHECK-NOT: G_CONSTANT i64
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_s8
@@ -944,19 +944,19 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r1
+ %2(p0) = COPY $r1
%3(s8) = G_LOAD %2 :: (load 1)
%4(s1) = G_ICMP intpred(ne), %1(s8), %3
; G_ICMP with s8 should widen
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
%5(s32) = G_ZEXT %4(s1)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_s16
@@ -975,19 +975,19 @@
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r1
+ %2(p0) = COPY $r1
%3(s16) = G_LOAD %2 :: (load 2)
%4(s1) = G_ICMP intpred(slt), %1(s16), %3
; G_ICMP with s16 should widen
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
%5(s32) = G_ZEXT %4(s1)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_s32
@@ -1004,16 +1004,16 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
; G_ICMP with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_s32
@@ -1030,16 +1030,16 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_CONSTANT i1 1
%3(s32) = G_SELECT %2(s1), %0, %1
; G_SELECT with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_ptr
@@ -1056,16 +1056,16 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(p0) = COPY %r0
- %1(p0) = COPY %r1
+ %0(p0) = COPY $r0
+ %1(p0) = COPY $r1
%2(s1) = G_CONSTANT i1 0
%3(p0) = G_SELECT %2(s1), %0, %1
; G_SELECT with p0 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
- %r0 = COPY %3(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_brcond
@@ -1082,10 +1082,10 @@
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
G_BRCOND %2(s1), %bb.1
; G_BRCOND with s1 is legal, so we should find it unchanged in the output
@@ -1093,12 +1093,12 @@
G_BR %bb.2
bb.1:
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
bb.2:
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -1117,13 +1117,13 @@
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
- %3(s32) = COPY %r2
+ %2(s32) = COPY $r1
+ %3(s32) = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1135,8 +1135,8 @@
%4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
; G_PHI with s32 is legal, so we should find it unchanged in the output
; CHECK: G_PHI {{%[0-9]+}}(s32), %bb.0, {{%[0-9]+}}(s32), %bb.1
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_p0
@@ -1154,13 +1154,13 @@
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(p0) = COPY %r1
- %3(p0) = COPY %r2
+ %2(p0) = COPY $r1
+ %3(p0) = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1172,8 +1172,8 @@
%4(p0) = G_PHI %2(p0), %bb.0, %3(p0), %bb.1
; G_PHI with p0 is legal, so we should find it unchanged in the output
; CHECK: G_PHI {{%[0-9]+}}(p0), %bb.0, {{%[0-9]+}}(p0), %bb.1
- %r0 = COPY %4(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_s64
@@ -1191,13 +1191,13 @@
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %d0, %d1
+ liveins: $r0, $d0, $d1
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s64) = COPY %d0
- %3(s64) = COPY %d1
+ %2(s64) = COPY $d0
+ %3(s64) = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1210,8 +1210,8 @@
; G_PHI with s64 is legal when we have floating point support, so we should
; find it unchanged in the output
; CHECK: G_PHI {{%[0-9]+}}(s64), %bb.0, {{%[0-9]+}}(s64), %bb.1
- %d0 = COPY %4(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %4(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_phi_s8
@@ -1232,18 +1232,18 @@
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
- ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
- %4(s32) = COPY %r2
+ %4(s32) = COPY $r2
%5(s8) = G_TRUNC %4(s32)
- ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+ ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[V1:%[0-9]+]]:_(s32) = COPY [[R1]]
@@ -1261,10 +1261,10 @@
; CHECK: [[V:%[0-9]+]]:_(s32) = G_PHI [[V1]](s32), %bb.0, [[V2]](s32), %bb.1
%7(s32) = G_ANYEXT %6(s8)
- %r0 = COPY %7(s32)
+ $r0 = COPY %7(s32)
; CHECK: [[R:%[0-9]+]]:_(s32) = COPY [[V]]
- ; CHECK: %r0 = COPY [[R]](s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]](s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_global_variable
@@ -1279,13 +1279,13 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_GLOBAL_VALUE @a_global
; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global
- %r0 = COPY %1(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(p0)
+ BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
index e7aaa74..f86ded1 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
@@ -6,16 +6,16 @@
define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_reg_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: %r1 = COPY [[AVREG]]
-; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $r0 = COPY [[BVREG]]
+; CHECK-DAG: $r1 = COPY [[AVREG]]
+; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $r0 = COPY [[RVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a)
ret i32 *%r
@@ -25,26 +25,26 @@
define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_stack_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: %r1 = COPY [[AVREG]]
-; CHECK-DAG: %r2 = COPY [[BVREG]]
-; CHECK-DAG: %r3 = COPY [[AVREG]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $r0 = COPY [[BVREG]]
+; CHECK-DAG: $r1 = COPY [[AVREG]]
+; CHECK-DAG: $r2 = COPY [[BVREG]]
+; CHECK-DAG: $r3 = COPY [[AVREG]]
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
-; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $r0 = COPY [[RVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
ret i32 *%r
@@ -54,53 +54,53 @@
define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
; CHECK-LABEL: name: test_call_ext_params
-; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]]
-; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
-; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
-; CHECK: ADJCALLSTACKDOWN 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 20, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
-; CHECK: %r0 = COPY [[SEXTA]]
+; CHECK: $r0 = COPY [[SEXTA]]
; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
-; CHECK: %r1 = COPY [[ZEXTA]]
+; CHECK: $r1 = COPY [[ZEXTA]]
; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16)
-; CHECK: %r2 = COPY [[SEXTB]]
+; CHECK: $r2 = COPY [[SEXTB]]
; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16)
-; CHECK: %r3 = COPY [[ZEXTB]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $r3 = COPY [[ZEXTB]]
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: [[SEXTA2:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]]
; CHECK: G_STORE [[SEXTA2]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: [[ZEXTA2:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]]
; CHECK: G_STORE [[ZEXTA2]](s32), [[FI2]](p0){{.*}}store 4
-; CHECK: [[SP3:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP3:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI3:%[0-9]+]]:_(p0) = G_GEP [[SP3]], [[OFF3]](s32)
; CHECK: [[SEXTB2:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]]
; CHECK: G_STORE [[SEXTB2]](s32), [[FI3]](p0){{.*}}store 4
-; CHECK: [[SP4:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP4:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[FI4:%[0-9]+]]:_(p0) = G_GEP [[SP4]], [[OFF4]](s32)
; CHECK: [[ZEXTB2:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]]
; CHECK: G_STORE [[ZEXTB2]](s32), [[FI4]](p0){{.*}}store 4
-; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_GEP [[SP5]], [[OFF5]](s32)
; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]]
; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4
-; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: BL @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]]
-; CHECK: ADJCALLSTACKUP 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 20, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
-; CHECK: %r0 = COPY [[RExtVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RExtVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c)
ret i16 %r
@@ -110,16 +110,16 @@
define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_vfpcc_fp_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %s0 = COPY [[BVREG]]
-; CHECK-DAG: %d1 = COPY [[AVREG]]
-; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
-; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %d0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %d0
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $s2
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $s0 = COPY [[BVREG]]
+; CHECK-DAG: $d1 = COPY [[AVREG]]
+; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
+; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $d0 = COPY [[RVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $d0
entry:
%r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a)
ret double %r
@@ -129,38 +129,38 @@
define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_aapcs_fp_params
-; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: ADJCALLSTACKDOWN 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: ADJCALLSTACKDOWN 16, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $r0 = COPY [[BVREG]]
; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
-; LITTLE-DAG: %r2 = COPY [[A1]]
-; LITTLE-DAG: %r3 = COPY [[A2]]
-; BIG-DAG: %r2 = COPY [[A2]]
-; BIG-DAG: %r3 = COPY [[A1]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; LITTLE-DAG: $r2 = COPY [[A1]]
+; LITTLE-DAG: $r3 = COPY [[A2]]
+; BIG-DAG: $r2 = COPY [[A2]]
+; BIG-DAG: $r3 = COPY [[A1]]
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8
-; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 16, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
-; LITTLE-DAG: %r0 = COPY [[R1]]
-; LITTLE-DAG: %r1 = COPY [[R2]]
-; BIG-DAG: %r0 = COPY [[R2]]
-; BIG-DAG: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; LITTLE-DAG: $r0 = COPY [[R1]]
+; LITTLE-DAG: $r1 = COPY [[R2]]
+; BIG-DAG: $r0 = COPY [[R2]]
+; BIG-DAG: $r1 = COPY [[R1]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a)
ret double %r
@@ -170,14 +170,14 @@
define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
; CHECK-LABEL: name: test_call_different_call_conv
-; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[X]]
-; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
-; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %s0 = COPY [[R]]
-; CHECK: BX_RET 14, %noreg, implicit %s0
+; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $r0 = COPY [[X]]
+; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
+; CHECK: [[R:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $s0 = COPY [[R]]
+; CHECK: BX_RET 14, $noreg, implicit $s0
entry:
%r = notail call arm_aapcscc float @different_call_conv_target(float %x)
ret float %r
@@ -187,28 +187,28 @@
define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
; CHECK-LABEL: name: test_tiny_int_arrays
-; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96)
; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
; that composite types larger than 4 bytes should be passed through memory),
; but it's what DAGISel does. We should fix it in the common code for both.
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1, implicit %r2
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1, implicit $r2
entry:
%r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr)
ret [3 x i32] %r
@@ -218,23 +218,23 @@
define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
; CHECK-LABEL: name: test_multiple_int_arrays
-; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64)
; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, %noreg
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: $r3 = COPY [[R3]]
+; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: BX_RET 14, $noreg
entry:
notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1)
ret void
@@ -249,35 +249,35 @@
; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: $r3 = COPY [[R3]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 56
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
-; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, %noreg
+; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
+; CHECK: ADJCALLSTACKUP 64, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: BX_RET 14, $noreg
entry:
notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr)
ret void
@@ -289,43 +289,43 @@
; CHECK-LABEL: name: test_fp_arrays_aapcs
; CHECK: fixedStack:
; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
-; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192)
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
-; LITTLE: %r0 = COPY [[ARR0_0]](s32)
-; LITTLE: %r1 = COPY [[ARR0_1]](s32)
-; BIG: %r0 = COPY [[ARR0_1]](s32)
-; BIG: %r1 = COPY [[ARR0_0]](s32)
+; LITTLE: $r0 = COPY [[ARR0_0]](s32)
+; LITTLE: $r1 = COPY [[ARR0_1]](s32)
+; BIG: $r0 = COPY [[ARR0_1]](s32)
+; BIG: $r1 = COPY [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
-; LITTLE: %r2 = COPY [[ARR1_0]](s32)
-; LITTLE: %r3 = COPY [[ARR1_1]](s32)
-; BIG: %r2 = COPY [[ARR1_1]](s32)
-; BIG: %r3 = COPY [[ARR1_0]](s32)
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; LITTLE: $r2 = COPY [[ARR1_0]](s32)
+; LITTLE: $r3 = COPY [[ARR1_1]](s32)
+; BIG: $r2 = COPY [[ARR1_1]](s32)
+; BIG: $r3 = COPY [[ARR1_0]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32)
; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8
-; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr)
ret [2 x float] %r
@@ -340,13 +340,13 @@
; CHECK-DAG: id: [[Z1_ID:[0-9]+]], type: default, offset: 8, size: 8,
; CHECK-DAG: id: [[Z2_ID:[0-9]+]], type: default, offset: 16, size: 8,
; CHECK-DAG: id: [[Z3_ID:[0-9]+]], type: default, offset: 24, size: 8,
-; CHECK: liveins: %d0, %d1, %d2, %s6, %s7, %s8
-; CHECK: [[X0:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK: [[X1:%[0-9]+]]:_(s64) = COPY %d1
-; CHECK: [[X2:%[0-9]+]]:_(s64) = COPY %d2
-; CHECK: [[Y0:%[0-9]+]]:_(s32) = COPY %s6
-; CHECK: [[Y1:%[0-9]+]]:_(s32) = COPY %s7
-; CHECK: [[Y2:%[0-9]+]]:_(s32) = COPY %s8
+; CHECK: liveins: $d0, $d1, $d2, $s6, $s7, $s8
+; CHECK: [[X0:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK: [[X1:%[0-9]+]]:_(s64) = COPY $d1
+; CHECK: [[X2:%[0-9]+]]:_(s64) = COPY $d2
+; CHECK: [[Y0:%[0-9]+]]:_(s32) = COPY $s6
+; CHECK: [[Y1:%[0-9]+]]:_(s32) = COPY $s7
+; CHECK: [[Y2:%[0-9]+]]:_(s32) = COPY $s8
; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8
; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
@@ -358,45 +358,45 @@
; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
-; CHECK: ADJCALLSTACKDOWN 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192)
; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96)
; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256)
-; CHECK: %d0 = COPY [[X0]](s64)
-; CHECK: %d1 = COPY [[X1]](s64)
-; CHECK: %d2 = COPY [[X2]](s64)
-; CHECK: %s6 = COPY [[Y0]](s32)
-; CHECK: %s7 = COPY [[Y1]](s32)
-; CHECK: %s8 = COPY [[Y2]](s32)
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $d0 = COPY [[X0]](s64)
+; CHECK: $d1 = COPY [[X1]](s64)
+; CHECK: $d2 = COPY [[X2]](s64)
+; CHECK: $s6 = COPY [[Y0]](s32)
+; CHECK: $s7 = COPY [[Y1]](s32)
+; CHECK: $s8 = COPY [[Y2]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[Z0_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z0_OFFSET]](s32)
; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z1_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[Z1_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z1_OFFSET]](s32)
; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[Z2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z2_OFFSET]](s32)
; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32)
; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8
-; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %s0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %s1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3
+; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $s1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $s2
+; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $s3
; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKUP 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 32, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128)
-; CHECK: %s0 = COPY [[R0]]
-; CHECK: %s1 = COPY [[R1]]
-; CHECK: %s2 = COPY [[R2]]
-; CHECK: %s3 = COPY [[R3]]
-; CHECK: BX_RET 14, %noreg, implicit %s0, implicit %s1, implicit %s2, implicit %s3
+; CHECK: $s0 = COPY [[R0]]
+; CHECK: $s1 = COPY [[R1]]
+; CHECK: $s2 = COPY [[R2]]
+; CHECK: $s3 = COPY [[R3]]
+; CHECK: BX_RET 14, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3
entry:
%r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
ret [4 x float] %r
@@ -411,41 +411,41 @@
; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: $r3 = COPY [[R3]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 72
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
-; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 80, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
ret [2 x i32*] %r
@@ -455,23 +455,23 @@
define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
; CHECK-LABEL: test_structs
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
-; CHECK-DAG: %r0 = COPY [[X0]](s32)
-; CHECK-DAG: %r1 = COPY [[X1]](s32)
-; CHECK: BL @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: $r0 = COPY [[X0]](s32)
+; CHECK-DAG: $r1 = COPY [[X1]](s32)
+; CHECK: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
-; CHECK: %r0 = COPY [[R0]](s32)
-; CHECK: %r1 = COPY [[R1]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK: $r0 = COPY [[R0]](s32)
+; CHECK: $r1 = COPY [[R1]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
%r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
ret {i32, i32} %r
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 8960fa9..f025dd0 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -101,13 +101,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ADD %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -127,13 +127,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SUB %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -153,13 +153,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_MUL %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -179,13 +179,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SDIV %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -205,13 +205,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_UDIV %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -231,13 +231,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_AND %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -257,13 +257,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_OR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -283,13 +283,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_XOR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -309,13 +309,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_LSHR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -335,13 +335,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ASHR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -361,13 +361,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SHL %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -395,15 +395,15 @@
- { id: 6, class: _ }
body: |
bb.0:
- liveins: %r0
- %0(p0) = COPY %r0
+ liveins: $r0
+ %0(p0) = COPY $r0
%6(s64) = G_LOAD %0 :: (load 8)
%1(s32) = G_LOAD %0 :: (load 4)
%2(s16) = G_LOAD %0 :: (load 2)
%3(s8) = G_LOAD %0 :: (load 1)
%4(s1) = G_LOAD %0 :: (load 1)
%5(p0) = G_LOAD %0 :: (load 4)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -431,9 +431,9 @@
- { id: 6, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r5, %d6
- %0(p0) = COPY %r0
- %1(s32) = COPY %r1
+ liveins: $r0, $r1, $r5, $d6
+ %0(p0) = COPY $r0
+ %1(s32) = COPY $r1
G_STORE %1(s32), %0 :: (store 4)
%2(s16) = G_TRUNC %1(s32)
G_STORE %2(s16), %0 :: (store 2)
@@ -441,11 +441,11 @@
G_STORE %3(s8), %0 :: (store 1)
%4(s1) = G_TRUNC %1(s32)
G_STORE %4(s1), %0 :: (store 1)
- %5(p0) = COPY %r5
+ %5(p0) = COPY $r5
G_STORE %5(p0), %0 :: (store 4)
- %6(s64) = COPY %d6
+ %6(s64) = COPY $d6
G_STORE %6(s64), %0 :: (store 8)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -473,12 +473,12 @@
%0(p0) = G_FRAME_INDEX %fixed-stack.0
%1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 0)
- %2(p0) = COPY %sp
+ %2(p0) = COPY $sp
%3(s32) = G_CONSTANT i32 8
%4(p0) = G_GEP %2, %3(s32)
G_STORE %1(s32), %4(p0) :: (store 4)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
@@ -498,13 +498,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
- %1(s32) = COPY %r1
+ %0(p0) = COPY $r0
+ %1(s32) = COPY $r1
%2(p0) = G_GEP %0, %1(s32)
- %r0 = COPY %2(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constants
@@ -519,8 +519,8 @@
body: |
bb.0:
%0(s32) = G_CONSTANT 42
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_inttoptr_s32
@@ -536,10 +536,10 @@
- { id: 1, class: _ }
body: |
bb.0:
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32)
- %r0 = COPY %1(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_ptrtoint_s32
@@ -555,10 +555,10 @@
- { id: 1, class: _ }
body: |
bb.0:
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0)
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_globals
@@ -573,8 +573,8 @@
body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @a_global
- %r0 = COPY %0(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_anyext_s8_32
@@ -592,13 +592,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8)
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_anyext_s16_32
@@ -616,13 +616,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16)
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_s32_16
@@ -640,13 +640,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %2(p0) = COPY %r1
+ %0(s32) = COPY $r0
+ %2(p0) = COPY $r1
%1(s16) = G_TRUNC %0(s32)
G_STORE %1(s16), %2 :: (store 2)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_trunc_s64_32
@@ -664,13 +664,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %d0
+ liveins: $r0, $d0
- %0(s64) = COPY %d0
- %2(p0) = COPY %r0
+ %0(s64) = COPY $d0
+ %2(p0) = COPY $r0
%1(s32) = G_TRUNC %0(s64)
G_STORE %1(s32), %2 :: (store 4)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_icmp_eq_s32
@@ -691,14 +691,14 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -720,14 +720,14 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -749,14 +749,14 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -780,15 +780,15 @@
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
%3(s1) = G_TRUNC %2(s32)
%4(s32) = G_SELECT %3(s1), %0, %1
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -808,18 +808,18 @@
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
bb.2:
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
@@ -844,13 +844,13 @@
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
- %3(s32) = COPY %r2
+ %2(s32) = COPY $r1
+ %3(s32) = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -860,8 +860,8 @@
bb.2:
%4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_s64
@@ -885,13 +885,13 @@
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %d0, %d1
+ liveins: $r0, $d0, $d1
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s64) = COPY %d0
- %3(s64) = COPY %d1
+ %2(s64) = COPY $d0
+ %3(s64) = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -901,8 +901,8 @@
bb.2:
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
- %d0 = COPY %4(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %4(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_fadd_s32
@@ -921,13 +921,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FADD %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -947,13 +947,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FADD %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -973,13 +973,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FSUB %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -999,13 +999,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FSUB %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1025,13 +1025,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FMUL %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1051,13 +1051,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FMUL %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1077,13 +1077,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FDIV %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1103,13 +1103,13 @@
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FDIV %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1126,12 +1126,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s32) = G_FNEG %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1148,12 +1148,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s64) = G_FNEG %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1174,14 +1174,14 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
%3(s32) = G_FMA %0, %1, %2
- %s0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
name: test_fma_s64
@@ -1201,14 +1201,14 @@
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = COPY %d2
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ %2(s64) = COPY $d2
%3(s64) = G_FMA %0, %1, %2
- %d0 = COPY %3(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %3(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_fpext_s32_to_s64
@@ -1224,12 +1224,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s64) = G_FPEXT %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_fptrunc_s64_to_s32
@@ -1245,12 +1245,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s32) = G_FPTRUNC %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
name: test_fptosi_s32
@@ -1266,12 +1266,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s32) = G_FPTOSI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -1288,12 +1288,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s32) = G_FPTOSI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s32
@@ -1309,12 +1309,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s32) = G_FPTOUI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -1331,12 +1331,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s32) = G_FPTOUI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_s32
@@ -1352,12 +1352,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_SITOFP %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1374,12 +1374,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s64) = G_SITOFP %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_uitofp_s32
@@ -1395,12 +1395,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_UITOFP %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1417,12 +1417,12 @@
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s64) = G_UITOFP %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_soft_fp_s64
@@ -1445,14 +1445,14 @@
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
- %r0 = COPY %3(s32)
- %r1 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %3(s32)
+ $r1 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
index 9045f31..017cbfd 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
@@ -18,13 +18,13 @@
body: |
bb.1:
; CHECK-LABEL: name: test_fptosi
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, %noreg
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, $noreg
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
- ; CHECK: %r0 = COPY [[COPY1]]
- ; CHECK: MOVPCLR 14, %noreg, implicit %r0
- %0:fprb(s32) = COPY %s0
+ ; CHECK: $r0 = COPY [[COPY1]]
+ ; CHECK: MOVPCLR 14, $noreg, implicit $r0
+ %0:fprb(s32) = COPY $s0
%1:gprb(s32) = G_FPTOSI %0(s32)
- %r0 = COPY %1(s32)
- MOVPCLR 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ MOVPCLR 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
index 60568d5..b198d7b 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
@@ -33,13 +33,13 @@
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_global
@@ -59,13 +59,13 @@
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_global :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_internal_constant
@@ -85,13 +85,13 @@
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_constant
@@ -111,11 +111,11 @@
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_constant :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
index dc48dee..b19239f 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
@@ -37,19 +37,19 @@
bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
- ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global
- ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
- ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
+ ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
+ ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_global
@@ -71,19 +71,19 @@
bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
- ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global
- ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
- ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
+ ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
+ ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_internal_constant
@@ -104,16 +104,16 @@
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
- ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_constant
@@ -134,14 +134,14 @@
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
- ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
index cd03d42..beb0bb5 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
@@ -26,18 +26,18 @@
bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
- ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_global
@@ -56,16 +56,16 @@
bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
- ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
index d2b4ffa..9866c4d 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
@@ -24,17 +24,17 @@
selected: false
body: |
bb.1 (%ir-block.0):
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0:fprb(s64) = COPY %d0
- %1:fprb(s64) = COPY %d1
- %2:fprb(s64) = COPY %d2
+ %0:fprb(s64) = COPY $d0
+ %1:fprb(s64) = COPY $d1
+ %2:fprb(s64) = COPY $d2
%3:fprb(s64) = G_FNEG %1
%4:fprb(s64) = G_FMA %0, %3, %2
%5:fprb(s64) = G_FNEG %4
- %d0 = COPY %5(s64)
- MOVPCLR 14, %noreg, implicit %d0
+ $d0 = COPY %5(s64)
+ MOVPCLR 14, $noreg, implicit $d0
-# CHECK: %{{[0-9]+}}:dpr = VFNMSD %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, 14, %noreg
+# CHECK: %{{[0-9]+}}:dpr = VFNMSD %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, 14, $noreg
...
diff --git a/llvm/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir b/llvm/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
index c9a88b6..30306fe 100644
--- a/llvm/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
+++ b/llvm/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
@@ -9,7 +9,7 @@
BX_RET 14, 0
bb.2:
- Bcc %bb.1, 1, %cpsr
+ Bcc %bb.1, 1, $cpsr
bb.3:
B %bb.1
diff --git a/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll b/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
index 0ec20c8..1dabb88 100644
--- a/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
+++ b/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
@@ -9,5 +9,5 @@
ret void
}
-; CHECK: tBL 14, %noreg, &__chkstk, implicit-def %lr, implicit %sp, implicit killed %r4, implicit-def %r4, implicit-def dead %r12, implicit-def dead %cpsr
+; CHECK: tBL 14, $noreg, &__chkstk, implicit-def $lr, implicit $sp, implicit killed $r4, implicit-def $r4, implicit-def dead $r12, implicit-def dead $cpsr
diff --git a/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir b/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
index 62675b4..8ff1847 100644
--- a/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
+++ b/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
@@ -32,8 +32,8 @@
- { id: 4, class: tgpr }
- { id: 5, class: tgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -49,27 +49,27 @@
hasVAStart: false
hasMustTailInVarArgFunc: false
-# CHECK: tMOVi8 1, 14, %noreg
-# CHECK: tMOVi8 0, 14, %noreg
-# CHECK: tMUL %1, %0, 14, %noreg
+# CHECK: tMOVi8 1, 14, $noreg
+# CHECK: tMOVi8 0, 14, $noreg
+# CHECK: tMUL %1, %0, 14, $noreg
# CHECK-NOT: tCMPi8
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
- %2, %cpsr = tMUL %1, %0, 14, %noreg
- %3, %cpsr = tMOVi8 1, 14, %noreg
- %4, %cpsr = tMOVi8 0, 14, %noreg
- tCMPi8 killed %2, 0, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.entry, 0, %cpsr
+ %1 = COPY $r1
+ %0 = COPY $r0
+ %2, $cpsr = tMUL %1, %0, 14, $noreg
+ %3, $cpsr = tMOVi8 1, 14, $noreg
+ %4, $cpsr = tMOVi8 0, 14, $noreg
+ tCMPi8 killed %2, 0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.entry, 0, $cpsr
bb.1.entry:
bb.2.entry:
%5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
- %r0 = COPY %5
- tBX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5
+ tBX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir b/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir
index 12569b5..c447fed 100644
--- a/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir
+++ b/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir
@@ -51,8 +51,8 @@
- { id: 4, class: tgpr }
- { id: 5, class: tgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -76,28 +76,28 @@
# CHECK-NEXT: tCMPi8
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
- %2, %cpsr = tMUL %0, %1, 14, %noreg
- tSTRspi %2, %stack.1.mul, 0, 14, %noreg :: (store 4 into %ir.mul)
- tCMPi8 %2, 0, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.if.end, 12, %cpsr
- tB %bb.1.if.then, 14, %noreg
+ %1 = COPY $r1
+ %0 = COPY $r0
+ %2, $cpsr = tMUL %0, %1, 14, $noreg
+ tSTRspi %2, %stack.1.mul, 0, 14, $noreg :: (store 4 into %ir.mul)
+ tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.if.end, 12, $cpsr
+ tB %bb.1.if.then, 14, $noreg
bb.1.if.then:
- %4, %cpsr = tMOVi8 42, 14, %noreg
- tSTRspi killed %4, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
- tB %bb.3.return, 14, %noreg
+ %4, $cpsr = tMOVi8 42, 14, $noreg
+ tSTRspi killed %4, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)
+ tB %bb.3.return, 14, $noreg
bb.2.if.end:
- %3, %cpsr = tMOVi8 1, 14, %noreg
- tSTRspi killed %3, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
+ %3, $cpsr = tMOVi8 1, 14, $noreg
+ tSTRspi killed %3, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)
bb.3.return:
- %5 = tLDRspi %stack.0.retval, 0, 14, %noreg :: (dereferenceable load 4 from %ir.retval)
- %r0 = COPY %5
- tBX_RET 14, %noreg, implicit %r0
+ %5 = tLDRspi %stack.0.retval, 0, 14, $noreg :: (dereferenceable load 4 from %ir.retval)
+ $r0 = COPY %5
+ tBX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/constant-islands-cfg.mir b/llvm/test/CodeGen/ARM/constant-islands-cfg.mir
index 140ef72..c83a4ad 100644
--- a/llvm/test/CodeGen/ARM/constant-islands-cfg.mir
+++ b/llvm/test/CodeGen/ARM/constant-islands-cfg.mir
@@ -15,7 +15,7 @@
tracksRegLiveness: true
registers:
liveins:
- - { reg: '%r0', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -37,7 +37,7 @@
# CHECK-LABEL: name: test_split_cfg
# CHECK: bb.0:
# CHECK: successors: %[[LONG_BR_BB:bb.[0-9]+]](0x{{[0-9a-f]+}}), %[[DEST1:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
-# CHECK: tBcc %[[LONG_BR_BB]], 0, %cpsr
+# CHECK: tBcc %[[LONG_BR_BB]], 0, $cpsr
# CHECK: tB %[[DEST1]]
# CHECK: [[LONG_BR_BB]]:
# CHECK: successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
@@ -47,18 +47,18 @@
body: |
bb.0:
- liveins: %r0
- tCMPi8 killed %r0, 0, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2, 1, killed %cpsr
- tB %bb.3, 14, %noreg
+ liveins: $r0
+ tCMPi8 killed $r0, 0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 1, killed $cpsr
+ tB %bb.3, 14, $noreg
bb.1:
- dead %r0 = SPACE 256, undef %r0
+ dead $r0 = SPACE 256, undef $r0
bb.2:
- tPOP_RET 14, %noreg, def %pc
+ tPOP_RET 14, $noreg, def $pc
bb.3:
- tPOP_RET 14, %noreg, def %pc
+ tPOP_RET 14, $noreg, def $pc
...
diff --git a/llvm/test/CodeGen/ARM/dbg-range-extension.mir b/llvm/test/CodeGen/ARM/dbg-range-extension.mir
index 02105ea..0aa81e9 100644
--- a/llvm/test/CodeGen/ARM/dbg-range-extension.mir
+++ b/llvm/test/CodeGen/ARM/dbg-range-extension.mir
@@ -23,37 +23,37 @@
# CHECK: [[VAR_I:![0-9]+]] = !DILocalVariable(name: "i",
# CHECK: bb.0.entry
-# CHECK: DBG_VALUE debug-use %r0, debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use %noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use $r0, debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_A:\$r[0-9]+]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_B:\$r[0-9]+]], debug-use $noreg, [[VAR_B]]
# CHECK: bb.1.if.then
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use %noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_C:\$r[0-9]+]], debug-use $noreg, [[VAR_C]]
# CHECK: DBG_VALUE 1, 0, [[VAR_I]]
# CHECK: bb.2.for.body
-# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use %noreg, [[VAR_I]]
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_I:\$r[0-9]+]], debug-use $noreg, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use $noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use $noreg, [[VAR_I]]
# CHECK: bb.3.for.cond
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use $noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use $noreg, [[VAR_I]]
# CHECK: bb.4.for.cond.cleanup
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use $noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
# CHECK: bb.5.if.end
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
--- |
; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll'
source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll"
@@ -171,21 +171,21 @@
selected: false
tracksRegLiveness: false
liveins:
- - { reg: '%r0' }
-calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
- '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
- '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
- '%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
- '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
- '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
- '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
- '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
- '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
- '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
- '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
- '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
- '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
- '%d11_d12_d13_d14' ]
+ - { reg: '$r0' }
+calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
+ '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
+ '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
+ '$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
+ '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
+ '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
+ '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
+ '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
+ '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
+ '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
+ '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
+ '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
+ '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
+ '$d11_d12_d13_d14' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -201,76 +201,76 @@
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
- - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r11' }
- - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%r7' }
- - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%r6' }
- - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%r5' }
- - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr' }
+ - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r11' }
+ - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '$r7' }
+ - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '$r6' }
+ - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '$r5' }
+ - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '$r4' }
body: |
bb.0.entry:
- liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
+ liveins: $r0, $r4, $r5, $r6, $r7, $r11, $lr
- %sp = frame-setup STMDB_UPD %sp, 14, %noreg, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
+ $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r11, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 24
- frame-setup CFI_INSTRUCTION offset %lr, -4
- frame-setup CFI_INSTRUCTION offset %r11, -8
- frame-setup CFI_INSTRUCTION offset %r7, -12
- frame-setup CFI_INSTRUCTION offset %r6, -16
- frame-setup CFI_INSTRUCTION offset %r5, -20
- frame-setup CFI_INSTRUCTION offset %r4, -24
- DBG_VALUE debug-use %r0, debug-use %noreg, !13, !20, debug-location !21
- %r4 = MOVr killed %r0, 14, %noreg, %noreg
- DBG_VALUE debug-use %r4, debug-use %noreg, !13, !20, debug-location !21
- %r0 = MOVi 10, 14, %noreg, _, debug-location !22
- %r1 = MOVi 11, 14, %noreg, _, debug-location !22
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22
- %r5 = MOVr killed %r0, 14, %noreg, _, debug-location !22
- DBG_VALUE debug-use %r5, debug-use %noreg, !14, !20, debug-location !23
- CMPri %r4, 0, 14, %noreg, implicit-def %cpsr, debug-location !25
- Bcc %bb.5.if.end, 0, killed %cpsr
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r11, -8
+ frame-setup CFI_INSTRUCTION offset $r7, -12
+ frame-setup CFI_INSTRUCTION offset $r6, -16
+ frame-setup CFI_INSTRUCTION offset $r5, -20
+ frame-setup CFI_INSTRUCTION offset $r4, -24
+ DBG_VALUE debug-use $r0, debug-use $noreg, !13, !20, debug-location !21
+ $r4 = MOVr killed $r0, 14, $noreg, $noreg
+ DBG_VALUE debug-use $r4, debug-use $noreg, !13, !20, debug-location !21
+ $r0 = MOVi 10, 14, $noreg, _, debug-location !22
+ $r1 = MOVi 11, 14, $noreg, _, debug-location !22
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def $r0, debug-location !22
+ $r5 = MOVr killed $r0, 14, $noreg, _, debug-location !22
+ DBG_VALUE debug-use $r5, debug-use $noreg, !14, !20, debug-location !23
+ CMPri $r4, 0, 14, $noreg, implicit-def $cpsr, debug-location !25
+ Bcc %bb.5.if.end, 0, killed $cpsr
bb.1.if.then:
- liveins: %r4, %r5
+ liveins: $r4, $r5
- %r0 = MOVi 12, 14, %noreg, _, debug-location !26
- %r1 = MOVi 13, 14, %noreg, _, debug-location !26
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26
- %r6 = MOVr killed %r0, 14, %noreg, _, debug-location !26
- DBG_VALUE debug-use %r6, debug-use %noreg, !15, !20, debug-location !27
- %r7 = MOVi 1, 14, %noreg, %noreg
+ $r0 = MOVi 12, 14, $noreg, _, debug-location !26
+ $r1 = MOVi 13, 14, $noreg, _, debug-location !26
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def $r0, debug-location !26
+ $r6 = MOVr killed $r0, 14, $noreg, _, debug-location !26
+ DBG_VALUE debug-use $r6, debug-use $noreg, !15, !20, debug-location !27
+ $r7 = MOVi 1, 14, $noreg, $noreg
DBG_VALUE 1, 0, !18, !20, debug-location !28
B %bb.3.for.cond
bb.2.for.body:
- liveins: %r4, %r5, %r6, %r7
+ liveins: $r4, $r5, $r6, $r7
- %r1 = ADDrr %r5, %r7, 14, %noreg, _, debug-location !36
- %r0 = MOVr %r7, 14, %noreg, _, debug-location !36
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36
- %r7 = ADDri killed %r7, 1, 14, %noreg, _, debug-location !38
- DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
+ $r1 = ADDrr $r5, $r7, 14, $noreg, _, debug-location !36
+ $r0 = MOVr $r7, 14, $noreg, _, debug-location !36
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0, debug-location !36
+ $r7 = ADDri killed $r7, 1, 14, $noreg, _, debug-location !38
+ DBG_VALUE debug-use $r7, debug-use $noreg, !18, !20, debug-location !28
bb.3.for.cond:
- liveins: %r4, %r5, %r6, %r7
+ liveins: $r4, $r5, $r6, $r7
- DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
- CMPrr %r7, %r4, 14, %noreg, implicit-def %cpsr, debug-location !33
- Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
+ DBG_VALUE debug-use $r7, debug-use $noreg, !18, !20, debug-location !28
+ CMPrr $r7, $r4, 14, $noreg, implicit-def $cpsr, debug-location !33
+ Bcc %bb.2.for.body, 11, killed $cpsr, debug-location !33
bb.4.for.cond.cleanup:
- liveins: %r4, %r5, %r6
+ liveins: $r4, $r5, $r6
- %r0 = MOVr %r5, 14, %noreg, _, debug-location !34
- %r1 = MOVr killed %r6, 14, %noreg, _, debug-location !34
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34
+ $r0 = MOVr $r5, 14, $noreg, _, debug-location !34
+ $r1 = MOVr killed $r6, 14, $noreg, _, debug-location !34
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0, debug-location !34
bb.5.if.end:
- liveins: %r4, %r5
+ liveins: $r4, $r5
- %r0 = MOVr killed %r5, 14, %noreg, _, debug-location !43
- %r1 = MOVr killed %r4, 14, %noreg, _, debug-location !43
- %sp = LDMIA_UPD %sp, 14, %noreg, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43
- TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43
+ $r0 = MOVr killed $r5, 14, $noreg, _, debug-location !43
+ $r1 = MOVr killed $r4, 14, $noreg, _, debug-location !43
+ $sp = LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r11, def $lr, debug-location !43
+ TAILJMPd @func2, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1, debug-location !43
...
diff --git a/llvm/test/CodeGen/ARM/debug-info-arg.ll b/llvm/test/CodeGen/ARM/debug-info-arg.ll
index b72dc5f..3b987f7 100644
--- a/llvm/test/CodeGen/ARM/debug-info-arg.ll
+++ b/llvm/test/CodeGen/ARM/debug-info-arg.ll
@@ -11,7 +11,7 @@
tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, metadata !13, metadata !DIExpression()), !dbg !21
tail call void @llvm.dbg.value(metadata i64 %x, metadata !14, metadata !DIExpression()), !dbg !22
tail call void @llvm.dbg.value(metadata i64 %y, metadata !17, metadata !DIExpression()), !dbg !23
-;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [%r7+0]
+;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [$r7+0]
tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, metadata !18, metadata !DIExpression()), !dbg !24
tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, metadata !19, metadata !DIExpression()), !dbg !25
%1 = icmp eq %struct.tag_s* %c, null, !dbg !26
diff --git a/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll b/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
index 15c153b..988df8b 100644
--- a/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
+++ b/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
@@ -5,8 +5,8 @@
;CHECK: vadd.f32 q4, q8, q8
;CHECK-NEXT: LBB0_1
-;CHECK: @DEBUG_VALUE: x <- %q4{{$}}
-;CHECK-NEXT: @DEBUG_VALUE: y <- %q4{{$}}
+;CHECK: @DEBUG_VALUE: x <- $q4{{$}}
+;CHECK-NEXT: @DEBUG_VALUE: y <- $q4{{$}}
;CHECK: beq LBB0_1
diff --git a/llvm/test/CodeGen/ARM/expand-pseudos.mir b/llvm/test/CodeGen/ARM/expand-pseudos.mir
index b35c2dc..e10471f 100644
--- a/llvm/test/CodeGen/ARM/expand-pseudos.mir
+++ b/llvm/test/CodeGen/ARM/expand-pseudos.mir
@@ -20,16 +20,16 @@
alignment: 2
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
- liveins: %r0
+ liveins: $r0
- %r1 = MOVi 2, 14, %noreg, %noreg
- CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
- %r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr
- %r0 = MOVr killed %r1, 14, %noreg, %noreg
- BX_RET 14, %noreg, implicit %r0
+ $r1 = MOVi 2, 14, $noreg, $noreg
+ CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
+ $r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr
+ $r0 = MOVr killed $r1, 14, $noreg, $noreg
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -37,16 +37,16 @@
alignment: 2
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
- liveins: %r0
+ liveins: $r0
- %r1 = MOVi 2, 14, %noreg, %noreg
- CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
- %r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr
- %r0 = MOVr killed %r1, 14, %noreg, %noreg
- BX_RET 14, %noreg, implicit %r0
+ $r1 = MOVi 2, 14, $noreg, $noreg
+ CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
+ $r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr
+ $r0 = MOVr killed $r1, 14, $noreg, $noreg
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -54,22 +54,22 @@
alignment: 2
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '' }
- - { reg: '%r1', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- CMPri %r1, 500, 14, %noreg, implicit-def %cpsr
- %r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr
- BX_RET 14, %noreg, implicit %r0
+ CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
+ $r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr
+ BX_RET 14, $noreg, implicit $r0
...
# CHECK-LABEL: name: test1
-# CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1
+# CHECK: $r1 = MOVi16 500, 0, killed $cpsr, implicit killed $r1
# CHECK-LABEL: name: test2
-# CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1
-# CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr
+# CHECK: $r1 = MOVi16 2068, 0, $cpsr, implicit killed $r1
+# CHECK: $r1 = MOVTi16 $r1, 7637, 0, $cpsr
# CHECK-LABEL: name: test3
-# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, %noreg, implicit killed %r0
+# CHECK: $r0 = MOVr killed $r1, 12, killed $cpsr, $noreg, implicit killed $r0
diff --git a/llvm/test/CodeGen/ARM/fpoffset_overflow.mir b/llvm/test/CodeGen/ARM/fpoffset_overflow.mir
index 59d981a..72a785b 100644
--- a/llvm/test/CodeGen/ARM/fpoffset_overflow.mir
+++ b/llvm/test/CodeGen/ARM/fpoffset_overflow.mir
@@ -3,10 +3,10 @@
# This should trigger an emergency spill in the register scavenger because the
# frame offset into the large argument is too large.
# CHECK-LABEL: name: func0
-# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, %noreg :: (store 4 into %stack.0)
-# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, %noreg, %noreg
-# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, %noreg :: (load 4)
-# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, %noreg :: (load 4 from %stack.0)
+# CHECK: t2STRi12 killed [[SPILLED:\$r[0-9]+]], $sp, 0, 14, $noreg :: (store 4 into %stack.0)
+# CHECK: [[SPILLED]] = t2ADDri killed $sp, 4096, 14, $noreg, $noreg
+# CHECK: $sp = t2LDRi12 killed [[SPILLED]], 40, 14, $noreg :: (load 4)
+# CHECK: [[SPILLED]] = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.0)
name: func0
tracksRegLiveness: true
fixedStack:
@@ -16,44 +16,44 @@
isAliased: false }
body: |
bb.0:
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r7 = IMPLICIT_DEF
- %r8 = IMPLICIT_DEF
- %r9 = IMPLICIT_DEF
- %r10 = IMPLICIT_DEF
- %r11 = IMPLICIT_DEF
- %r12 = IMPLICIT_DEF
- %lr = IMPLICIT_DEF
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r7 = IMPLICIT_DEF
+ $r8 = IMPLICIT_DEF
+ $r9 = IMPLICIT_DEF
+ $r10 = IMPLICIT_DEF
+ $r11 = IMPLICIT_DEF
+ $r12 = IMPLICIT_DEF
+ $lr = IMPLICIT_DEF
- %sp = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
+ $sp = t2LDRi12 %fixed-stack.0, 0, 14, $noreg :: (load 4)
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r7
- KILL %r8
- KILL %r9
- KILL %r10
- KILL %r11
- KILL %r12
- KILL %lr
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r7
+ KILL $r8
+ KILL $r9
+ KILL $r10
+ KILL $r11
+ KILL $r12
+ KILL $lr
...
---
# This should not trigger an emergency spill yet.
# CHECK-LABEL: name: func1
# CHECK-NOT: t2STRi12
# CHECK-NOT: t2ADDri
-# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, %noreg :: (load 4)
+# CHECK: $r11 = t2LDRi12 $sp, 4092, 14, $noreg :: (load 4)
# CHECK-NOT: t2LDRi12
name: func1
tracksRegLiveness: true
@@ -64,33 +64,33 @@
isAliased: false }
body: |
bb.0:
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r8 = IMPLICIT_DEF
- %r9 = IMPLICIT_DEF
- %r10 = IMPLICIT_DEF
- %r11 = IMPLICIT_DEF
- %r12 = IMPLICIT_DEF
- %lr = IMPLICIT_DEF
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r8 = IMPLICIT_DEF
+ $r9 = IMPLICIT_DEF
+ $r10 = IMPLICIT_DEF
+ $r11 = IMPLICIT_DEF
+ $r12 = IMPLICIT_DEF
+ $lr = IMPLICIT_DEF
- %r11 = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
+ $r11 = t2LDRi12 %fixed-stack.0, 0, 14, $noreg :: (load 4)
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r8
- KILL %r9
- KILL %r10
- KILL %r11
- KILL %r12
- KILL %lr
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r8
+ KILL $r9
+ KILL $r10
+ KILL $r11
+ KILL $r12
+ KILL $lr
...
diff --git a/llvm/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir b/llvm/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir
index 90d606a..99e82e7 100644
--- a/llvm/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir
@@ -10,12 +10,12 @@
bb.1:
successors: %bb.2, %bb.4
- Bcc %bb.4, 1, %cpsr
+ Bcc %bb.4, 1, $cpsr
bb.2:
successors: %bb.3, %bb.5
- Bcc %bb.5, 1, %cpsr
+ Bcc %bb.5, 1, $cpsr
bb.3:
successors: %bb.5
@@ -28,7 +28,7 @@
bb.5:
successors: %bb.1, %bb.6
- Bcc %bb.1, 1, %cpsr
+ Bcc %bb.1, 1, $cpsr
bb.6:
BX_RET 14, _
diff --git a/llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir b/llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
index 6b7ad20..3061eb3 100644
--- a/llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
@@ -3,19 +3,19 @@
name: foo
body: |
bb.0:
- Bcc %bb.2, 1, %cpsr
+ Bcc %bb.2, 1, $cpsr
bb.1:
- %sp = tADDspi %sp, 1, 14, _
+ $sp = tADDspi $sp, 1, 14, _
B %bb.3
bb.2:
- %sp = tADDspi %sp, 2, 14, _
+ $sp = tADDspi $sp, 2, 14, _
B %bb.3
bb.3:
successors:
- %sp = tADDspi %sp, 3, 14, _
+ $sp = tADDspi $sp, 3, 14, _
BX_RET 14, _
...
@@ -24,7 +24,7 @@
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
-# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
-# CHECK: %sp = tADDspi %sp, 3, 14, %noreg
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr
+# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp
+# CHECK: $sp = tADDspi $sp, 3, 14, $noreg
+# CHECK: BX_RET 14, $noreg
diff --git a/llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir b/llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
index f5f09a8..60dcbd9 100644
--- a/llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
@@ -3,28 +3,28 @@
name: foo
body: |
bb.0:
- Bcc %bb.2, 1, %cpsr
+ Bcc %bb.2, 1, $cpsr
bb.1:
successors: %bb.3(0x20000000), %bb.4(0x60000000)
- %sp = tADDspi %sp, 1, 14, _
- Bcc %bb.3, 1, %cpsr
+ $sp = tADDspi $sp, 1, 14, _
+ Bcc %bb.3, 1, $cpsr
B %bb.4
bb.2:
successors: %bb.3(0x20000000), %bb.4(0x60000000)
- %sp = tADDspi %sp, 2, 14, _
- Bcc %bb.3, 1, %cpsr
+ $sp = tADDspi $sp, 2, 14, _
+ Bcc %bb.3, 1, $cpsr
B %bb.4
bb.3:
successors:
- %sp = tADDspi %sp, 3, 14, _
+ $sp = tADDspi $sp, 3, 14, _
BX_RET 14, _
bb.4:
successors:
- %sp = tADDspi %sp, 4, 14, _
+ $sp = tADDspi $sp, 4, 14, _
BX_RET 14, _
...
@@ -35,14 +35,14 @@
# CHECK: bb.0:
# CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000)
-# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
-# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
-# CHECK: Bcc %bb.2, 1, %cpsr
+# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr
+# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp
+# CHECK: Bcc %bb.2, 1, $cpsr
# CHECK: bb.1:
-# CHECK: %sp = tADDspi %sp, 4, 14, %noreg
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 4, 14, $noreg
+# CHECK: BX_RET 14, $noreg
# CHECK: bb.2:
-# CHECK: %sp = tADDspi %sp, 3, 14, %noreg
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 3, 14, $noreg
+# CHECK: BX_RET 14, $noreg
diff --git a/llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir b/llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
index 13ba94f..92738e1 100644
--- a/llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
@@ -5,16 +5,16 @@
bb.0:
bb.1:
- Bcc %bb.3, 0, %cpsr
+ Bcc %bb.3, 0, $cpsr
bb.2:
bb.3:
- Bcc %bb.1, 0, %cpsr
+ Bcc %bb.1, 0, $cpsr
bb.4:
successors: %bb.1
- tBRIND %r1, 14, _
+ tBRIND $r1, 14, _
...
# We should only get bb.1 as successor to bb.1. No zero percent probability
@@ -27,7 +27,7 @@
# CHECK: bb.1:
# CHECK: successors: %bb.1(0x80000000)
# CHECK-NOT: %bb.2(0x00000000)
-# CHECK: tBRIND %r1, 1, %cpsr
+# CHECK: tBRIND $r1, 1, $cpsr
# CHECK: B %bb.1
#CHECK-NOT: bb.2:
diff --git a/llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir b/llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
index 8d1c71a..1856853 100644
--- a/llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
@@ -3,7 +3,7 @@
name: foo
body: |
bb.0:
- Bcc %bb.2, 0, %cpsr
+ Bcc %bb.2, 0, $cpsr
bb.1:
successors:
@@ -11,7 +11,7 @@
bb.2:
successors:
- %sp = tADDspi %sp, 2, 14, _
+ $sp = tADDspi $sp, 2, 14, _
BX_RET 14, _
...
@@ -19,7 +19,7 @@
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: %sp = tADDspi %sp, 2, 0, %cpsr
-# CHECK: BX_RET 0, %cpsr
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 2, 0, $cpsr
+# CHECK: BX_RET 0, $cpsr
+# CHECK: BX_RET 14, $noreg
diff --git a/llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir b/llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
index 92ecbc8..a2a3180 100644
--- a/llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
@@ -12,21 +12,21 @@
body: |
bb.0:
- Bcc %bb.1, 1, %cpsr
+ Bcc %bb.1, 1, $cpsr
B %bb.2
bb.1:
- Bcc %bb.3, 0, %cpsr
+ Bcc %bb.3, 0, $cpsr
bb.2:
successors:
- tBL 14, %cpsr, @__stack_chk_fail
+ tBL 14, $cpsr, @__stack_chk_fail
bb.3:
successors:
- %sp = tADDspi %sp, 2, 14, _
- %sp = tADDspi %sp, 2, 14, _
- tTAILJMPdND @bar, 14, %cpsr
+ $sp = tADDspi $sp, 2, 14, _
+ $sp = tADDspi $sp, 2, 14, _
+ tTAILJMPdND @bar, 14, $cpsr
...
# bb.2 has no successors, presumably because __stack_chk_fail doesn't return,
@@ -38,15 +38,15 @@
# CHECK: bb.0:
# CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
-# CHECK: Bcc %bb.2, 1, %cpsr
+# CHECK: Bcc %bb.2, 1, $cpsr
# CHECK: bb.1:
# CHECK-NOT: successors: %bb
-# CHECK: tBL 14, %cpsr, @__stack_chk_fail
+# CHECK: tBL 14, $cpsr, @__stack_chk_fail
# CHECK: bb.2:
# CHECK-NOT: successors: %bb
-# CHECK: tBL 1, %cpsr, @__stack_chk_fail
-# CHECK: %sp = tADDspi %sp, 2, 14, %noreg
-# CHECK: %sp = tADDspi %sp, 2, 14, %noreg
-# CHECK: tTAILJMPdND @bar, 14, %cpsr
+# CHECK: tBL 1, $cpsr, @__stack_chk_fail
+# CHECK: $sp = tADDspi $sp, 2, 14, $noreg
+# CHECK: $sp = tADDspi $sp, 2, 14, $noreg
+# CHECK: tTAILJMPdND @bar, 14, $cpsr
diff --git a/llvm/test/CodeGen/ARM/imm-peephole-arm.mir b/llvm/test/CodeGen/ARM/imm-peephole-arm.mir
index 0457507..27b099b10 100644
--- a/llvm/test/CodeGen/ARM/imm-peephole-arm.mir
+++ b/llvm/test/CodeGen/ARM/imm-peephole-arm.mir
@@ -1,6 +1,6 @@
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
-# CHECK: [[IN:%.*]]:gprnopc = COPY %r0
+# CHECK: [[IN:%.*]]:gprnopc = COPY $r0
# CHECK: [[SUM1TMP:%.*]]:rgpr = ADDri [[IN]], 133
# CHECK: [[SUM1:%.*]]:rgpr = ADDri killed [[SUM1TMP]], 25600
@@ -35,25 +35,25 @@
- { id: 7, class: rgpr }
- { id: 8, class: rgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
+ - { reg: '$r0', virtual-reg: '%0' }
body: |
bb.0 (%ir-block.0):
- liveins: %r0
+ liveins: $r0
- %0 = COPY %r0
+ %0 = COPY $r0
%1 = MOVi32imm -25733
- %2 = SUBrr %0, killed %1, 14, %noreg, %noreg
+ %2 = SUBrr %0, killed %1, 14, $noreg, $noreg
%3 = MOVi32imm 25733
- %4 = SUBrr %0, killed %3, 14, %noreg, %noreg
+ %4 = SUBrr %0, killed %3, 14, $noreg, $noreg
%5 = MOVi32imm -25733
- %6 = ADDrr %0, killed %5, 14, %noreg, %noreg
+ %6 = ADDrr %0, killed %5, 14, $noreg, $noreg
%7 = MOVi32imm 25733
- %8 = ADDrr killed %0, killed %7, 14, %noreg, %noreg
+ %8 = ADDrr killed %0, killed %7, 14, $noreg, $noreg
- %r0 = COPY killed %8
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY killed %8
+ BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/imm-peephole-thumb.mir b/llvm/test/CodeGen/ARM/imm-peephole-thumb.mir
index 04e2b19..f75533c 100644
--- a/llvm/test/CodeGen/ARM/imm-peephole-thumb.mir
+++ b/llvm/test/CodeGen/ARM/imm-peephole-thumb.mir
@@ -1,6 +1,6 @@
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
-# CHECK: [[IN:%.*]]:gprnopc = COPY %r0
+# CHECK: [[IN:%.*]]:gprnopc = COPY $r0
# CHECK: [[SUM1TMP:%.*]]:rgpr = t2ADDri [[IN]], 25600
# CHECK: [[SUM1:%.*]]:rgpr = t2ADDri killed [[SUM1TMP]], 133
@@ -35,24 +35,24 @@
- { id: 7, class: rgpr }
- { id: 8, class: rgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
+ - { reg: '$r0', virtual-reg: '%0' }
body: |
bb.0 (%ir-block.0):
- liveins: %r0
- %0 = COPY %r0
+ liveins: $r0
+ %0 = COPY $r0
%1 = t2MOVi32imm -25733
- %2 = t2SUBrr %0, killed %1, 14, %noreg, %noreg
+ %2 = t2SUBrr %0, killed %1, 14, $noreg, $noreg
%3 = t2MOVi32imm 25733
- %4 = t2SUBrr %0, killed %3, 14, %noreg, %noreg
+ %4 = t2SUBrr %0, killed %3, 14, $noreg, $noreg
%5 = t2MOVi32imm -25733
- %6= t2ADDrr %0, killed %5, 14, %noreg, %noreg
+ %6= t2ADDrr %0, killed %5, 14, $noreg, $noreg
%7 = t2MOVi32imm 25733
- %8 = t2ADDrr killed %0, killed %7, 14, %noreg, %noreg
+ %8 = t2ADDrr killed %0, killed %7, 14, $noreg, $noreg
- %r0 = COPY killed %8
- tBX_RET 14, %noreg, implicit %r0
+ $r0 = COPY killed %8
+ tBX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/load_store_opt_kill.mir b/llvm/test/CodeGen/ARM/load_store_opt_kill.mir
index 85cc595..2c3324a 100644
--- a/llvm/test/CodeGen/ARM/load_store_opt_kill.mir
+++ b/llvm/test/CodeGen/ARM/load_store_opt_kill.mir
@@ -2,11 +2,11 @@
---
# CHECK-LABEL: name: f
name: f
-# Make sure the load into %r0 doesn't clobber the base register before the second load uses it.
-# CHECK: %r3 = LDRi12 %r0, 12, 14, %noreg
-# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, %noreg
+# Make sure the load into $r0 doesn't clobber the base register before the second load uses it.
+# CHECK: $r3 = LDRi12 $r0, 12, 14, $noreg
+# CHECK-NEXT: $r0 = LDRi12 $r0, 8, 14, $noreg
body: |
bb.0:
- liveins: %r0, %r3
- %r0, %r3 = LDRD %r0, %noreg, 8, 14, %noreg
+ liveins: $r0, $r3
+ $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg
...
diff --git a/llvm/test/CodeGen/ARM/machine-copyprop.mir b/llvm/test/CodeGen/ARM/machine-copyprop.mir
index bb9c347..56722cf 100644
--- a/llvm/test/CodeGen/ARM/machine-copyprop.mir
+++ b/llvm/test/CodeGen/ARM/machine-copyprop.mir
@@ -3,20 +3,20 @@
# Test that machine copy prop recognizes the implicit-def operands on a COPY
# as clobbering the register.
# CHECK-LABEL: name: func
-# CHECK: %d2 = VMOVv2i32 2, 14, %noreg
-# CHECK: %s5 = COPY %s0, implicit %q1, implicit-def %q1
-# CHECK: VST1q32 %r0, 0, %q1, 14, %noreg
+# CHECK: $d2 = VMOVv2i32 2, 14, $noreg
+# CHECK: $s5 = COPY $s0, implicit $q1, implicit-def $q1
+# CHECK: VST1q32 $r0, 0, $q1, 14, $noreg
# The following two COPYs must not be removed
-# CHECK: %s4 = COPY %s20, implicit-def %q1
-# CHECK: %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
-# CHECK: VST1q32 %r2, 0, %q1, 14, %noreg
+# CHECK: $s4 = COPY $s20, implicit-def $q1
+# CHECK: $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1
+# CHECK: VST1q32 $r2, 0, $q1, 14, $noreg
name: func
body: |
bb.0:
- %d2 = VMOVv2i32 2, 14, %noreg
- %s5 = COPY %s0, implicit %q1, implicit-def %q1
- VST1q32 %r0, 0, %q1, 14, %noreg
- %s4 = COPY %s20, implicit-def %q1
- %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
- VST1q32 %r2, 0, %q1, 14, %noreg
+ $d2 = VMOVv2i32 2, 14, $noreg
+ $s5 = COPY $s0, implicit $q1, implicit-def $q1
+ VST1q32 $r0, 0, $q1, 14, $noreg
+ $s4 = COPY $s20, implicit-def $q1
+ $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1
+ VST1q32 $r2, 0, $q1, 14, $noreg
...
diff --git a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
index 8b8f3f0..ea8cecc 100644
--- a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
+++ b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
@@ -42,57 +42,57 @@
# CHECK_SWIFT: Latency : 2
# CHECK_R52: Latency : 2
#
-# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, %noreg; mem:LD4[@g1](dereferenceable)
+# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, $noreg; mem:LD4[@g1](dereferenceable)
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 3
# CHECK_R52: Latency : 4
#
-# CHECK : SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, %noreg, %noreg
+# CHECK : SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
-# CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, %noreg
+# CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, $noreg
# CHECK_A9: Latency : 0
# CHECK_SWIFT: Latency : 14
# CHECK_R52: Latency : 8
-# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, %noreg; mem:ST4[@g1]
+# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, $noreg; mem:ST4[@g1]
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 0
# CHECK_R52: Latency : 4
#
-# CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, %noreg
+# CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, %noreg
+# CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, %noreg
+# CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, $noreg
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
#
-# CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, %noreg
+# CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, %noreg
+# CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, %noreg
+# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, $noreg
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 5
# CHECK_R52: Latency : 4
#
-# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr, %20:rgpr, 14, %noreg
+# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr, %20:rgpr, 14, $noreg
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 7
# CHECK_R52: Latency : 4
@@ -129,8 +129,8 @@
- { id: 19, class: rgpr }
- { id: 20, class: rgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -147,29 +147,29 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
+ %1 = COPY $r1
+ %0 = COPY $r0
%2 = t2MOVi32imm @g1
- %3 = t2LDRi12 %2, 0, 14, %noreg :: (dereferenceable load 4 from @g1)
+ %3 = t2LDRi12 %2, 0, 14, $noreg :: (dereferenceable load 4 from @g1)
%4 = t2MOVi32imm @g2
- %5 = t2LDRi12 %4, 0, 14, %noreg :: (dereferenceable load 4 from @g2)
- %6 = t2ADDrr %3, %3, 14, %noreg, %noreg
- %7 = t2SDIV %6, %5, 14, %noreg
- t2STRi12 %7, %2, 0, 14, %noreg :: (store 4 into @g1)
- %8 = t2SMULBB %1, %1, 14, %noreg
- %9 = t2SMLABB %0, %0, %8, 14, %noreg
- %10 = t2UXTH %9, 0, 14, %noreg
- %11 = t2MUL %10, %7, 14, %noreg
- %12 = t2MLA %11, %11, %11, 14, %noreg
- %13, %14 = t2UMULL %12, %12, 14, %noreg
- %19, %16 = t2UMULL %13, %13, 14, %noreg
- %17 = t2MLA %13, %14, %16, 14, %noreg
- %20 = t2MLA %13, %14, %17, 14, %noreg
- %19, %20 = t2UMLAL %12, %12, %19, %20, 14, %noreg
- %r0 = COPY %19
- %r1 = COPY %20
- tBX_RET 14, %noreg, implicit %r0, implicit %r1
+ %5 = t2LDRi12 %4, 0, 14, $noreg :: (dereferenceable load 4 from @g2)
+ %6 = t2ADDrr %3, %3, 14, $noreg, $noreg
+ %7 = t2SDIV %6, %5, 14, $noreg
+ t2STRi12 %7, %2, 0, 14, $noreg :: (store 4 into @g1)
+ %8 = t2SMULBB %1, %1, 14, $noreg
+ %9 = t2SMLABB %0, %0, %8, 14, $noreg
+ %10 = t2UXTH %9, 0, 14, $noreg
+ %11 = t2MUL %10, %7, 14, $noreg
+ %12 = t2MLA %11, %11, %11, 14, $noreg
+ %13, %14 = t2UMULL %12, %12, 14, $noreg
+ %19, %16 = t2UMULL %13, %13, 14, $noreg
+ %17 = t2MLA %13, %14, %16, 14, $noreg
+ %20 = t2MLA %13, %14, %17, 14, $noreg
+ %19, %20 = t2UMLAL %12, %12, %19, %20, 14, $noreg
+ $r0 = COPY %19
+ $r1 = COPY %20
+ tBX_RET 14, $noreg, implicit $r0, implicit $r1
...
diff --git a/llvm/test/CodeGen/ARM/misched-int-basic.mir b/llvm/test/CodeGen/ARM/misched-int-basic.mir
index 0428ea9..ec607d1 100644
--- a/llvm/test/CodeGen/ARM/misched-int-basic.mir
+++ b/llvm/test/CodeGen/ARM/misched-int-basic.mir
@@ -28,37 +28,37 @@
}
# CHECK: ********** MI Scheduling **********
-# CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, %noreg
+# CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, %noreg
+# CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, %noreg
+# CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
#
-# CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, $noreg, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, $noreg, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, $noreg, $noreg
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 5
# CHECK_R52: Latency : 4
#
-# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc, 14, $noreg, $noreg
# CHECK_SWIFT: Latency : 7
# CHECK_A9: Latency : 3
# CHECK_R52: Latency : 4
@@ -89,8 +89,8 @@
- { id: 13, class: gpr }
- { id: 14, class: gprnopc }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -107,22 +107,22 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
- %2 = SMULBB %1, %1, 14, %noreg
- %3 = SMLABB %0, %0, %2, 14, %noreg
- %4 = UXTH %3, 0, 14, %noreg
- %5 = MUL %4, %4, 14, %noreg, %noreg
- %6 = MLA %5, %5, %5, 14, %noreg, %noreg
- %7, %8 = UMULL %6, %6, 14, %noreg, %noreg
- %13, %10 = UMULL %7, %7, 14, %noreg, %noreg
- %11 = MLA %7, %8, %10, 14, %noreg, %noreg
- %14 = MLA %7, %8, %11, 14, %noreg, %noreg
- %13, %14 = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg
- %r0 = COPY %13
- %r1 = COPY %14
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ %1 = COPY $r1
+ %0 = COPY $r0
+ %2 = SMULBB %1, %1, 14, $noreg
+ %3 = SMLABB %0, %0, %2, 14, $noreg
+ %4 = UXTH %3, 0, 14, $noreg
+ %5 = MUL %4, %4, 14, $noreg, $noreg
+ %6 = MLA %5, %5, %5, 14, $noreg, $noreg
+ %7, %8 = UMULL %6, %6, 14, $noreg, $noreg
+ %13, %10 = UMULL %7, %7, 14, $noreg, $noreg
+ %11 = MLA %7, %8, %10, 14, $noreg, $noreg
+ %14 = MLA %7, %8, %11, 14, $noreg, $noreg
+ %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg
+ $r0 = COPY %13
+ $r1 = COPY %14
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
diff --git a/llvm/test/CodeGen/ARM/peephole-phi.mir b/llvm/test/CodeGen/ARM/peephole-phi.mir
index 54ae011..df0ffa6 100644
--- a/llvm/test/CodeGen/ARM/peephole-phi.mir
+++ b/llvm/test/CodeGen/ARM/peephole-phi.mir
@@ -7,39 +7,39 @@
# CHECK-LABEL: name: func
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: Bcc %bb.2, 1, undef %cpsr
+# CHECK: Bcc %bb.2, 1, undef $cpsr
#
# CHECK: bb.1:
# CHECK: %0:dpr = IMPLICIT_DEF
-# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, %noreg
+# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, $noreg
# CHECK: B %bb.3
#
# CHECK: bb.2:
# CHECK: %3:spr = IMPLICIT_DEF
-# CHECK: %4:gpr = VMOVRS %3, 14, %noreg
+# CHECK: %4:gpr = VMOVRS %3, 14, $noreg
#
# CHECK: bb.3:
# CHECK: %5:gpr = PHI %1, %bb.1, %4, %bb.2
-# CHECK: %6:spr = VMOVSR %5, 14, %noreg
+# CHECK: %6:spr = VMOVSR %5, 14, $noreg
---
name: func0
tracksRegLiveness: true
body: |
bb.0:
- Bcc %bb.2, 1, undef %cpsr
+ Bcc %bb.2, 1, undef $cpsr
bb.1:
%0:dpr = IMPLICIT_DEF
- %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, %noreg
+ %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
B %bb.3
bb.2:
%3:spr = IMPLICIT_DEF
- %4:gpr = VMOVRS %3:spr, 14, %noreg
+ %4:gpr = VMOVRS %3:spr, 14, $noreg
bb.3:
%5:gpr = PHI %1, %bb.1, %4, %bb.2
- %6:spr = VMOVSR %5, 14, %noreg
+ %6:spr = VMOVSR %5, 14, $noreg
...
# CHECK-LABEL: name: func1
@@ -50,20 +50,20 @@
tracksRegLiveness: true
body: |
bb.0:
- Bcc %bb.2, 1, undef %cpsr
+ Bcc %bb.2, 1, undef $cpsr
bb.1:
%1:spr = IMPLICIT_DEF
- %0:gpr = VMOVRS %1, 14, %noreg
+ %0:gpr = VMOVRS %1, 14, $noreg
B %bb.3
bb.2:
%3:spr = IMPLICIT_DEF
- %2:gpr = VMOVRS %3:spr, 14, %noreg
+ %2:gpr = VMOVRS %3:spr, 14, $noreg
bb.3:
%4:gpr = PHI %0, %bb.1, %2, %bb.2
- %5:spr = VMOVSR %4, 14, %noreg
+ %5:spr = VMOVSR %4, 14, $noreg
...
# The current implementation doesn't perform any transformations if undef
@@ -71,33 +71,33 @@
# CHECK-LABEL: name: func-undefops
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: Bcc %bb.2, 1, undef %cpsr
+# CHECK: Bcc %bb.2, 1, undef $cpsr
#
# CHECK: bb.1:
-# CHECK: %0:gpr = VMOVRS undef %1:spr, 14, %noreg
+# CHECK: %0:gpr = VMOVRS undef %1:spr, 14, $noreg
# CHECK: B %bb.3
#
# CHECK: bb.2:
-# CHECK: %2:gpr = VMOVRS undef %3:spr, 14, %noreg
+# CHECK: %2:gpr = VMOVRS undef %3:spr, 14, $noreg
#
# CHECK: bb.3:
# CHECK: %4:gpr = PHI %0, %bb.1, %2, %bb.2
-# CHECK: %5:spr = VMOVSR %4, 14, %noreg
+# CHECK: %5:spr = VMOVSR %4, 14, $noreg
---
name: func-undefops
tracksRegLiveness: true
body: |
bb.0:
- Bcc %bb.2, 1, undef %cpsr
+ Bcc %bb.2, 1, undef $cpsr
bb.1:
- %0:gpr = VMOVRS undef %1:spr, 14, %noreg
+ %0:gpr = VMOVRS undef %1:spr, 14, $noreg
B %bb.3
bb.2:
- %2:gpr = VMOVRS undef %3:spr, 14, %noreg
+ %2:gpr = VMOVRS undef %3:spr, 14, $noreg
bb.3:
%4:gpr = PHI %0, %bb.1, %2, %bb.2
- %5:spr = VMOVSR %4, 14, %noreg
+ %5:spr = VMOVSR %4, 14, $noreg
...
diff --git a/llvm/test/CodeGen/ARM/pei-swiftself.mir b/llvm/test/CodeGen/ARM/pei-swiftself.mir
index d2d3469..5228fbb 100644
--- a/llvm/test/CodeGen/ARM/pei-swiftself.mir
+++ b/llvm/test/CodeGen/ARM/pei-swiftself.mir
@@ -17,44 +17,44 @@
- { id: 1, type: default, size: 4096, alignment: 8 }
body: |
bb.0:
- liveins: %r10 ; swiftself parameter comes in as %r10
+ liveins: $r10 ; swiftself parameter comes in as $r10
; Bring up register pressure to force emergency spilling, coax scavenging
- ; to use %r10 as that one is not spilled/restored.
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r7 = IMPLICIT_DEF
- %r8 = IMPLICIT_DEF
- %r9 = IMPLICIT_DEF
- %r11 = IMPLICIT_DEF
- %r12 = IMPLICIT_DEF
- %lr = IMPLICIT_DEF
+ ; to use $r10 as that one is not spilled/restored.
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r7 = IMPLICIT_DEF
+ $r8 = IMPLICIT_DEF
+ $r9 = IMPLICIT_DEF
+ $r11 = IMPLICIT_DEF
+ $r12 = IMPLICIT_DEF
+ $lr = IMPLICIT_DEF
; Computing the large stack offset requires an extra register. We should
- ; not just use %r10 for that.
- ; CHECK-NOT: STRi12 %1,{{.*}}%r10
+ ; not just use $r10 for that.
+ ; CHECK-NOT: STRi12 %1,{{.*}}$r10
- STRi12 %r1, %stack.0, 0, 14, %noreg :: (store 4)
+ STRi12 $r1, %stack.0, 0, 14, $noreg :: (store 4)
; use the swiftself parameter value.
- KILL %r10
+ KILL $r10
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r7
- KILL %r8
- KILL %r9
- KILL %r11
- KILL %r12
- KILL %lr
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r7
+ KILL $r8
+ KILL $r9
+ KILL $r11
+ KILL $r12
+ KILL $lr
...
diff --git a/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir b/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir
index cc32008..67fff94 100644
--- a/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir
+++ b/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir
@@ -18,23 +18,23 @@
alignment: 1
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 : gpr = COPY %r1
- %0 : gpr = COPY %r0
- %2 : gpr = t2LDRi12 %1, 0, 14, %noreg :: (load 4 from %ir.y)
- t2STRi12 killed %2, %0, 0, 14, %noreg :: (store 4 into %ir.x)
- %3 : gpr = t2LDRi12 %1, 4, 14, %noreg :: (load 4 from %ir.arrayidx2)
- t2STRi12 killed %3, %0, 4, 14, %noreg :: (store 4 into %ir.arrayidx3)
+ %1 : gpr = COPY $r1
+ %0 : gpr = COPY $r0
+ %2 : gpr = t2LDRi12 %1, 0, 14, $noreg :: (load 4 from %ir.y)
+ t2STRi12 killed %2, %0, 0, 14, $noreg :: (store 4 into %ir.x)
+ %3 : gpr = t2LDRi12 %1, 4, 14, $noreg :: (load 4 from %ir.arrayidx2)
+ t2STRi12 killed %3, %0, 4, 14, $noreg :: (store 4 into %ir.arrayidx3)
; CHECK: t2LDRi12
; CHECK-NEXT: t2LDRi12
; CHECK-NEXT: t2STRi12
; CHECK-NEXT: t2STRi12
- tBX_RET 14, %noreg
+ tBX_RET 14, $noreg
...
diff --git a/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir b/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir
index c0202eb..f05bae4 100644
--- a/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir
+++ b/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir
@@ -18,24 +18,24 @@
alignment: 1
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
- - { reg: '%r2', virtual-reg: '%2' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
+ - { reg: '$r2', virtual-reg: '%2' }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %2 : rgpr = COPY %r2
- %1 : rgpr = COPY %r1
- %0 : gpr = COPY %r0
- %3 : rgpr = t2MUL %2, %2, 14, %noreg
- %4 : rgpr = t2MUL %1, %1, 14, %noreg
+ %2 : rgpr = COPY $r2
+ %1 : rgpr = COPY $r1
+ %0 : gpr = COPY $r0
+ %3 : rgpr = t2MUL %2, %2, 14, $noreg
+ %4 : rgpr = t2MUL %1, %1, 14, $noreg
%5 : rgpr = t2MOVi32imm -858993459
- %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg
- %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg
- t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
- %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
- t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
+ %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, $noreg
+ %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, $noreg
+ t2STRi12 %1, %0, 0, 14, $noreg :: (store 4)
+ %10 : rgpr = t2LSLri %2, 1, 14, $noreg, $noreg
+ t2STRi12 killed %10, %0, 4, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location.
@@ -44,38 +44,38 @@
; CHECK-NEXT: t2MOVi
; CHECK-NEXT: t2ADDrs
- %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
- %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
- t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
- %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
- t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
+ %11 : rgpr = t2MOVi 55, 14, $noreg, $noreg
+ %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, $noreg, $noreg
+ t2STRi12 killed %12, %0, 16, 14, $noreg :: (store 4)
+ %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, $noreg, $noreg
+ t2STRi12 killed %13, %0, 20, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 killed %12,
; CHECK-NEXT: t2STRi12 killed %13,
- tBX_RET 14, %noreg
+ tBX_RET 14, $noreg
---
# CHECK-LABEL: name: b
name: b
alignment: 1
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
- - { reg: '%r2', virtual-reg: '%2' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
+ - { reg: '$r2', virtual-reg: '%2' }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %2 : rgpr = COPY %r2
- %1 : rgpr = COPY %r1
- %0 : gpr = COPY %r0
- t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
- %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
- t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
- %3 : rgpr = t2MUL %2, %2, 14, %noreg
- t2STRi12 %3, %0, 8, 14, %noreg :: (store 4)
+ %2 : rgpr = COPY $r2
+ %1 : rgpr = COPY $r1
+ %0 : gpr = COPY $r0
+ t2STRi12 %1, %0, 0, 14, $noreg :: (store 4)
+ %10 : rgpr = t2LSLri %2, 1, 14, $noreg, $noreg
+ t2STRi12 killed %10, %0, 4, 14, $noreg :: (store 4)
+ %3 : rgpr = t2MUL %2, %2, 14, $noreg
+ t2STRi12 %3, %0, 8, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location.
@@ -85,21 +85,21 @@
; CHECK-NEXT: t2MUL
; CHECK-NEXT: t2MOVi32imm
- %4 : rgpr = t2MUL %1, %1, 14, %noreg
+ %4 : rgpr = t2MUL %1, %1, 14, $noreg
%5 : rgpr = t2MOVi32imm -858993459
- %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg
- %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg
- %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
- %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
- %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
- t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
- %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
- t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
+ %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, $noreg
+ %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, $noreg
+ %10 : rgpr = t2LSLri %2, 1, 14, $noreg, $noreg
+ %11 : rgpr = t2MOVi 55, 14, $noreg, $noreg
+ %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, $noreg, $noreg
+ t2STRi12 killed %12, %0, 16, 14, $noreg :: (store 4)
+ %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, $noreg, $noreg
+ t2STRi12 killed %13, %0, 20, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 {{.*}}, 16
; CHECK-NEXT: t2STRi12 {{.*}}, 20
- tBX_RET 14, %noreg
+ tBX_RET 14, $noreg
...
diff --git a/llvm/test/CodeGen/ARM/scavenging.mir b/llvm/test/CodeGen/ARM/scavenging.mir
index c7fb7b3..5e0cbfb 100644
--- a/llvm/test/CodeGen/ARM/scavenging.mir
+++ b/llvm/test/CodeGen/ARM/scavenging.mir
@@ -3,64 +3,64 @@
# CHECK-LABEL: name: scavengebug0
# Make sure we are not spilling/using a physreg used in the very last
# instruction of the scavenging range.
-# CHECK-NOT: tSTRi {{.*}}%r0,{{.*}}%r0
-# CHECK-NOT: tSTRi {{.*}}%r1,{{.*}}%r1
-# CHECK-NOT: tSTRi {{.*}}%r2,{{.*}}%r2
-# CHECK-NOT: tSTRi {{.*}}%r3,{{.*}}%r3
-# CHECK-NOT: tSTRi {{.*}}%r4,{{.*}}%r4
-# CHECK-NOT: tSTRi {{.*}}%r5,{{.*}}%r5
-# CHECK-NOT: tSTRi {{.*}}%r6,{{.*}}%r6
-# CHECK-NOT: tSTRi {{.*}}%r7,{{.*}}%r7
+# CHECK-NOT: tSTRi {{.*}}$r0,{{.*}}$r0
+# CHECK-NOT: tSTRi {{.*}}$r1,{{.*}}$r1
+# CHECK-NOT: tSTRi {{.*}}$r2,{{.*}}$r2
+# CHECK-NOT: tSTRi {{.*}}$r3,{{.*}}$r3
+# CHECK-NOT: tSTRi {{.*}}$r4,{{.*}}$r4
+# CHECK-NOT: tSTRi {{.*}}$r5,{{.*}}$r5
+# CHECK-NOT: tSTRi {{.*}}$r6,{{.*}}$r6
+# CHECK-NOT: tSTRi {{.*}}$r7,{{.*}}$r7
name: scavengebug0
body: |
bb.0:
; Bring up register pressure to force emergency spilling
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r7 = IMPLICIT_DEF
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r7 = IMPLICIT_DEF
%0 : tgpr = IMPLICIT_DEF
- %0 = tADDhirr %0, %sp, 14, %noreg
- tSTRi %r0, %0, 0, 14, %noreg
+ %0 = tADDhirr %0, $sp, 14, $noreg
+ tSTRi $r0, %0, 0, 14, $noreg
%1 : tgpr = IMPLICIT_DEF
- %1 = tADDhirr %1, %sp, 14, %noreg
- tSTRi %r1, %1, 0, 14, %noreg
+ %1 = tADDhirr %1, $sp, 14, $noreg
+ tSTRi $r1, %1, 0, 14, $noreg
%2 : tgpr = IMPLICIT_DEF
- %2 = tADDhirr %2, %sp, 14, %noreg
- tSTRi %r2, %2, 0, 14, %noreg
+ %2 = tADDhirr %2, $sp, 14, $noreg
+ tSTRi $r2, %2, 0, 14, $noreg
%3 : tgpr = IMPLICIT_DEF
- %3 = tADDhirr %3, %sp, 14, %noreg
- tSTRi %r3, %3, 0, 14, %noreg
+ %3 = tADDhirr %3, $sp, 14, $noreg
+ tSTRi $r3, %3, 0, 14, $noreg
%4 : tgpr = IMPLICIT_DEF
- %4 = tADDhirr %4, %sp, 14, %noreg
- tSTRi %r4, %4, 0, 14, %noreg
+ %4 = tADDhirr %4, $sp, 14, $noreg
+ tSTRi $r4, %4, 0, 14, $noreg
%5 : tgpr = IMPLICIT_DEF
- %5 = tADDhirr %5, %sp, 14, %noreg
- tSTRi %r5, %5, 0, 14, %noreg
+ %5 = tADDhirr %5, $sp, 14, $noreg
+ tSTRi $r5, %5, 0, 14, $noreg
%6 : tgpr = IMPLICIT_DEF
- %6 = tADDhirr %6, %sp, 14, %noreg
- tSTRi %r6, %6, 0, 14, %noreg
+ %6 = tADDhirr %6, $sp, 14, $noreg
+ tSTRi $r6, %6, 0, 14, $noreg
%7 : tgpr = IMPLICIT_DEF
- %7 = tADDhirr %7, %sp, 14, %noreg
- tSTRi %r7, %7, 0, 14, %noreg
+ %7 = tADDhirr %7, $sp, 14, $noreg
+ tSTRi $r7, %7, 0, 14, $noreg
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r7
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r7
diff --git a/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir
index c09c2db..b70c3e5 100644
--- a/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir
+++ b/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir
@@ -32,9 +32,9 @@
; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or
; hopefully, triggering an assert).
- ; CHECK: BUNDLE implicit-def dead %itstate
- ; CHECK: * DBG_VALUE debug-use %r1, debug-use %noreg, !"u"
- ; CHECK-NOT: * DBG_VALUE killed %r1, %noreg, !"u"
+ ; CHECK: BUNDLE implicit-def dead $itstate
+ ; CHECK: * DBG_VALUE debug-use $r1, debug-use $noreg, !"u"
+ ; CHECK-NOT: * DBG_VALUE killed $r1, $noreg, !"u"
declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1
@@ -92,24 +92,24 @@
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
- - { reg: '%r2' }
- - { reg: '%r3' }
-calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
- '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
- '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
- '%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
- '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
- '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
- '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
- '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
- '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
- '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
- '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
- '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
- '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
- '%d11_d12_d13_d14' ]
+ - { reg: '$r0' }
+ - { reg: '$r1' }
+ - { reg: '$r2' }
+ - { reg: '$r3' }
+calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
+ '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
+ '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
+ '$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
+ '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
+ '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
+ '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
+ '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
+ '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
+ '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
+ '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
+ '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
+ '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
+ '$d11_d12_d13_d14' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -125,33 +125,33 @@
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false }
+ - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2, %r3, %lr, %r7
+ liveins: $r0, $r1, $r2, $r3, $lr, $r7
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- %r0 = t2MOVi -1, 3, %cpsr, %noreg, implicit undef %r0
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- tBX_RET 3, %cpsr, implicit %r0, debug-location !34
- %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ t2CMPri $r3, 4, 14, $noreg, implicit-def $cpsr, debug-location !31
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ $r0 = t2MOVi -1, 3, $cpsr, $noreg, implicit undef $r0
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ tBX_RET 3, $cpsr, implicit $r0, debug-location !34
+ $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8
- frame-setup CFI_INSTRUCTION offset %lr, -4
- frame-setup CFI_INSTRUCTION offset %r7, -8
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- %r1 = tMOVr killed %r2, 14, %noreg, debug-location !32
- %r2 = tMOVr killed %r3, 14, %noreg, debug-location !32
- tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
- %r0 = t2MOVi 0, 14, %noreg, %noreg
- %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ $r1 = tMOVr killed $r2, 14, $noreg, debug-location !32
+ $r2 = tMOVr killed $r3, 14, $noreg, debug-location !32
+ tBL 14, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !32
+ $r0 = t2MOVi 0, 14, $noreg, $noreg
+ $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/single-issue-r52.mir b/llvm/test/CodeGen/ARM/single-issue-r52.mir
index 2275159..ba43f02 100644
--- a/llvm/test/CodeGen/ARM/single-issue-r52.mir
+++ b/llvm/test/CodeGen/ARM/single-issue-r52.mir
@@ -20,13 +20,13 @@
# CHECK: ********** MI Scheduling **********
# CHECK: ScheduleDAGMILive::schedule starting
-# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, %noreg; mem:LD32[%A](align=8)
+# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, $noreg; mem:LD32[%A](align=8)
# CHECK: Latency : 8
# CHECK: Single Issue : true;
-# CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, %noreg
+# CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, $noreg
# CHECK: Latency : 5
# CHECK: Single Issue : false;
-# CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, %noreg
+# CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg
# CHECK: Latency : 4
# CHECK: Single Issue : false;
@@ -56,7 +56,7 @@
- { id: 5, class: gpr }
- { id: 6, class: gpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
+ - { reg: '$r0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -73,14 +73,14 @@
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.0):
- liveins: %r0
+ liveins: $r0
- %0 = COPY %r0
- %1 = VLD4d8Pseudo %0, 8, 14, %noreg :: (load 32 from %ir.A, align 8)
- %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, %noreg
- %5, %6 = VMOVRRD %4, 14, %noreg
- %r0 = COPY %5
- %r1 = COPY %6
- BX_RET 14, %noreg, implicit %r0, implicit killed %r1
+ %0 = COPY $r0
+ %1 = VLD4d8Pseudo %0, 8, 14, $noreg :: (load 32 from %ir.A, align 8)
+ %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, $noreg
+ %5, %6 = VMOVRRD %4, 14, $noreg
+ $r0 = COPY %5
+ $r1 = COPY %6
+ BX_RET 14, $noreg, implicit $r0, implicit killed $r1
...
diff --git a/llvm/test/CodeGen/ARM/tail-dup-bundle.mir b/llvm/test/CodeGen/ARM/tail-dup-bundle.mir
index 719d616..f4760f2 100644
--- a/llvm/test/CodeGen/ARM/tail-dup-bundle.mir
+++ b/llvm/test/CodeGen/ARM/tail-dup-bundle.mir
@@ -2,35 +2,35 @@
---
# CHECK-LABEL: name: func
# Make sure the bundle gets duplicated correctly
-# CHECK: BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
-# CHECK: t2IT 1, 24, implicit-def %itstate
-# CHECK: t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
+# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
+# CHECK: t2IT 1, 24, implicit-def $itstate
+# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
# CHECK: }
-# CHECK: BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
-# CHECK: t2IT 1, 24, implicit-def %itstate
-# CHECK: t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
+# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
+# CHECK: t2IT 1, 24, implicit-def $itstate
+# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
# CHECK: }
name: func
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0, %lr, %r7
+ liveins: $r0, $lr, $r7
bb.1:
- liveins: %r0
+ liveins: $r0
- t2CMPri %r0, 32, 14, %noreg, implicit-def %cpsr
- BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
- t2IT 1, 24, implicit-def %itstate
- t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
+ t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr
+ BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
+ t2IT 1, 24, implicit-def $itstate
+ t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
}
- t2Bcc %bb.3, 1, killed %cpsr
+ t2Bcc %bb.3, 1, killed $cpsr
bb.2:
- %r0 = IMPLICIT_DEF
- t2B %bb.1, 14, %noreg
+ $r0 = IMPLICIT_DEF
+ t2B %bb.1, 14, $noreg
bb.3:
- %r0 = IMPLICIT_DEF
- t2B %bb.1, 14, %noreg
+ $r0 = IMPLICIT_DEF
+ t2B %bb.1, 14, $noreg
...
diff --git a/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll b/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll
index f3c83f0..d61b1d8 100644
--- a/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll
+++ b/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll
@@ -22,6 +22,6 @@
declare void @g(i32)
; CHECK-LABEL: name: foo
-; CHECK: [[BASE:%r[0-7]]], {{.*}} tADDi8
+; CHECK: [[BASE:\$r[0-7]]], {{.*}} tADDi8
; CHECK-NOT: [[BASE]] = tLDMIA_UPD {{.*}} [[BASE]]
; CHECK: tLDMIA killed [[BASE]], {{.*}} def [[BASE]]
diff --git a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir
index 52a39ff..0c6204a 100644
--- a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir
+++ b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir
@@ -12,7 +12,7 @@
# CHECK: JUMPTABLE_ADDRS
# CHECK-LABEL: name: bar
-# CHECK: tTBB_JT %pc, killed %r1
+# CHECK: tTBB_JT $pc, killed $r1
--- |
; ModuleID = 'simple.ll'
@@ -195,8 +195,8 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
+ - { reg: '$r0' }
+ - { reg: '$r1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -229,24 +229,24 @@
body: |
bb.0 (%ir-block.0):
successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %r2 = tLDRpci %const.0, 14, %noreg
- tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
- dead %r1 = SPACE 980, undef %r0
- %r0 = tUXTB killed %r0, 14, %noreg
- %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
- tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.d1, 8, killed %cpsr
+ $r2 = tLDRpci %const.0, 14, $noreg
+ tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store 4 into %ir.addr)
+ dead $r1 = SPACE 980, undef $r0
+ $r0 = tUXTB killed $r0, 14, $noreg
+ $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
+ tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.d1, 8, killed $cpsr
bb.1 (%ir-block.0):
successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
- liveins: %r1
+ liveins: $r1
- %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
- %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
- %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
- tBR_JTr killed %r0, %jump-table.0
+ $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
+ $r1 = tLEApcrelJT %jump-table.0, 14, $noreg
+ $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load 4 from jump-table)
+ tBR_JTr killed $r0, %jump-table.0
bb.3.d2:
@@ -293,8 +293,8 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
+ - { reg: '$r0' }
+ - { reg: '$r1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -327,23 +327,23 @@
body: |
bb.0 (%ir-block.0):
successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %r2 = tLDRpci %const.0, 14, %noreg
- tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
- %r0 = tUXTB killed %r0, 14, %noreg
- %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
- tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.d1, 8, killed %cpsr
+ $r2 = tLDRpci %const.0, 14, $noreg
+ tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store 4 into %ir.addr)
+ $r0 = tUXTB killed $r0, 14, $noreg
+ $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
+ tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.d1, 8, killed $cpsr
bb.1 (%ir-block.0):
successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
- liveins: %r1
+ liveins: $r1
- %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
- %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
- %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
- tBR_JTr killed %r0, %jump-table.0
+ $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
+ $r1 = tLEApcrelJT %jump-table.0, 14, $noreg
+ $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load 4 from jump-table)
+ tBR_JTr killed $r0, %jump-table.0
bb.3.d2:
diff --git a/llvm/test/CodeGen/ARM/virtregrewriter-subregliveness.mir b/llvm/test/CodeGen/ARM/virtregrewriter-subregliveness.mir
index 44bc856..3b8922f 100644
--- a/llvm/test/CodeGen/ARM/virtregrewriter-subregliveness.mir
+++ b/llvm/test/CodeGen/ARM/virtregrewriter-subregliveness.mir
@@ -22,18 +22,18 @@
- { id: 0, class: gprpair }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; That copy is being coalesced so we should use a KILL
; placeholder. If that's not a kill that means we probably
- ; not coalescing %0 and %r0_r1 and thus we are not testing
+ ; not coalescing %0 and $r0_r1 and thus we are not testing
; the problematic code anymore.
;
- ; CHECK: %r0 = KILL %r0, implicit killed %r0_r1, implicit-def %r0_r1
- ; CHECK-NEXT: %r1 = KILL %r1, implicit killed %r0_r1
- undef %0.gsub_0 = COPY %r0
- %0.gsub_1 = COPY %r1
- tBX_RET 14, %noreg, implicit %0
+ ; CHECK: $r0 = KILL $r0, implicit killed $r0_r1, implicit-def $r0_r1
+ ; CHECK-NEXT: $r1 = KILL $r1, implicit killed $r0_r1
+ undef %0.gsub_0 = COPY $r0
+ %0.gsub_1 = COPY $r1
+ tBX_RET 14, $noreg, implicit %0
...
@@ -48,14 +48,14 @@
- { id: 0, class: gprpair }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; r1 is not live through so check we are not implicitly using
; the big register.
- ; CHECK: %r0 = KILL %r0, implicit-def %r0_r1
+ ; CHECK: $r0 = KILL $r0, implicit-def $r0_r1
; CHECK-NEXT: tBX_RET
- undef %0.gsub_0 = COPY %r0
- tBX_RET 14, %noreg, implicit %0
+ undef %0.gsub_0 = COPY $r0
+ tBX_RET 14, $noreg, implicit %0
...
@@ -71,14 +71,14 @@
- { id: 0, class: gprpair }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; r1 is not live through so check we are not implicitly using
; the big register.
- ; CHECK: %r0 = KILL %r0, implicit-def %r1, implicit-def %r0_r1
+ ; CHECK: $r0 = KILL $r0, implicit-def $r1, implicit-def $r0_r1
; CHECK-NEXT: tBX_RET
- undef %0.gsub_0 = COPY %r0, implicit-def %r1
- tBX_RET 14, %noreg, implicit %0
+ undef %0.gsub_0 = COPY $r0, implicit-def $r1
+ tBX_RET 14, $noreg, implicit %0
...
diff --git a/llvm/test/CodeGen/ARM/vldm-liveness.mir b/llvm/test/CodeGen/ARM/vldm-liveness.mir
index c06342c..9f2f45d 100644
--- a/llvm/test/CodeGen/ARM/vldm-liveness.mir
+++ b/llvm/test/CodeGen/ARM/vldm-liveness.mir
@@ -21,20 +21,20 @@
name: foo
alignment: 1
liveins:
- - { reg: '%r0' }
+ - { reg: '$r0' }
body: |
bb.0 (%ir-block.0):
- liveins: %r0
+ liveins: $r0
- %s1 = VLDRS %r0, 1, 14, %noreg, implicit-def %q0 :: (load 4)
- %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
- ; CHECK: %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed undef %q0, implicit-def %q0 :: (load 4)
+ $s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load 4)
+ $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
+ ; CHECK: $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4)
- %s0 = VLDRS %r0, 0, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
- ; CHECK: VLDMSIA %r0, 14, %noreg, def %s0, def %s1, implicit-def %noreg
+ $s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
+ ; CHECK: VLDMSIA $r0, 14, $noreg, def $s0, def $s1, implicit-def $noreg
- %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
- ; CHECK: %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
+ $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
+ ; CHECK: $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
- tBX_RET 14, %noreg, implicit %q0
+ tBX_RET 14, $noreg, implicit $q0
...