Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html
In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.
llvm-svn: 323922
diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
index 4a870b7..778e08a 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
@@ -62,17 +62,17 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%a0_64' }
- - { reg: '%t9_64' }
-calleeSavedRegisters: [ '%fp', '%gp', '%ra', '%d12', '%d13', '%d14', '%d15',
- '%f24', '%f25', '%f26', '%f27', '%f28', '%f29',
- '%f30', '%f31', '%fp_64', '%f_hi24', '%f_hi25',
- '%f_hi26', '%f_hi27', '%f_hi28', '%f_hi29', '%f_hi30',
- '%f_hi31', '%gp_64', '%ra_64', '%s0', '%s1', '%s2',
- '%s3', '%s4', '%s5', '%s6', '%s7', '%d24_64', '%d25_64',
- '%d26_64', '%d27_64', '%d28_64', '%d29_64', '%d30_64',
- '%d31_64', '%s0_64', '%s1_64', '%s2_64', '%s3_64',
- '%s4_64', '%s5_64', '%s6_64', '%s7_64' ]
+ - { reg: '$a0_64' }
+ - { reg: '$t9_64' }
+calleeSavedRegisters: [ '$fp', '$gp', '$ra', '$d12', '$d13', '$d14', '$d15',
+ '$f24', '$f25', '$f26', '$f27', '$f28', '$f29',
+ '$f30', '$f31', '$fp_64', '$f_hi24', '$f_hi25',
+ '$f_hi26', '$f_hi27', '$f_hi28', '$f_hi29', '$f_hi30',
+ '$f_hi31', '$gp_64', '$ra_64', '$s0', '$s1', '$s2',
+ '$s3', '$s4', '$s5', '$s6', '$s7', '$d24_64', '$d25_64',
+ '$d26_64', '$d27_64', '$d28_64', '$d29_64', '$d30_64',
+ '$d31_64', '$s0_64', '$s1_64', '$s2_64', '$s3_64',
+ '$s4_64', '$s5_64', '$s6_64', '$s7_64' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -90,69 +90,69 @@
stack:
- { id: 0, name: retval, offset: -28, size: 4, alignment: 4 }
- { id: 1, name: a.addr, offset: -32, size: 4, alignment: 4 }
- - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%ra_64' }
- - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp_64' }
- - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%gp_64' }
+ - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '$ra_64' }
+ - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '$fp_64' }
+ - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$gp_64' }
body: |
bb.0.entry:
successors: %bb.1.if.then(0x40000000), %bb.5.if.else(0x40000000)
- liveins: %a0_64, %t9_64, %ra_64, %fp_64, %gp_64
+ liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
- %sp_64 = DADDiu %sp_64, -32
+ $sp_64 = DADDiu $sp_64, -32
CFI_INSTRUCTION def_cfa_offset 32
- SD killed %ra_64, %sp_64, 24 :: (store 8 into %stack.2)
- SD killed %fp_64, %sp_64, 16 :: (store 8 into %stack.3)
- SD killed %gp_64, %sp_64, 8 :: (store 8 into %stack.4)
- CFI_INSTRUCTION offset %ra_64, -8
- CFI_INSTRUCTION offset %fp_64, -16
- CFI_INSTRUCTION offset %gp_64, -24
- CFI_INSTRUCTION def_cfa_register %fp_64
- %at_64 = LUi64 @f
- %v0_64 = DADDu killed %at_64, %t9_64
- SW %a0, %sp_64, 0 :: (store 4 into %ir.a.addr)
- BGTZC %a0, %bb.5.if.else, implicit-def %at
+ SD killed $ra_64, $sp_64, 24 :: (store 8 into %stack.2)
+ SD killed $fp_64, $sp_64, 16 :: (store 8 into %stack.3)
+ SD killed $gp_64, $sp_64, 8 :: (store 8 into %stack.4)
+ CFI_INSTRUCTION offset $ra_64, -8
+ CFI_INSTRUCTION offset $fp_64, -16
+ CFI_INSTRUCTION offset $gp_64, -24
+ CFI_INSTRUCTION def_cfa_register $fp_64
+ $at_64 = LUi64 @f
+ $v0_64 = DADDu killed $at_64, $t9_64
+ SW $a0, $sp_64, 0 :: (store 4 into %ir.a.addr)
+ BGTZC $a0, %bb.5.if.else, implicit-def $at
bb.1.if.then:
successors: %bb.6.return(0x40000000), %bb.2.if.then(0x40000000)
- liveins: %a0
+ liveins: $a0
- BLTZC %a0, %bb.6.return, implicit-def %at
+ BLTZC $a0, %bb.6.return, implicit-def $at
bb.2.if.then:
successors: %bb.3.if.else(0x80000000)
- %t8 = IMPLICIT_DEF
+ $t8 = IMPLICIT_DEF
bb.3.if.else:
successors: %bb.6.return(0x40000000), %bb.4.if.else(0x40000000)
- liveins: %t8
+ liveins: $t8
- BLEZC %t8, %bb.6.return, implicit-def %at
+ BLEZC $t8, %bb.6.return, implicit-def $at
bb.4.if.else:
successors: %bb.6.return(0x80000000)
- liveins: %t8
+ liveins: $t8
- %at = LW %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
- %at = ADDu killed %at, %t8
- SW killed %at, %sp_64, 4 :: (store 4 into %ir.retval)
- J %bb.6.return, implicit-def dead %at
+ $at = LW $sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
+ $at = ADDu killed $at, $t8
+ SW killed $at, $sp_64, 4 :: (store 4 into %ir.retval)
+ J %bb.6.return, implicit-def dead $at
bb.5.if.else:
successors: %bb.6.return(0x80000000)
- liveins: %v0_64
+ liveins: $v0_64
- %gp_64 = DADDiu killed %v0_64, @f
- %a0_64 = LW64 %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
- %t9_64 = LD %gp_64, @g :: (load 8 from call-entry @g)
- JALR64Pseudo %t9_64, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- SW killed %v0, %sp_64, 4 :: (store 4 into %ir.retval)
+ $gp_64 = DADDiu killed $v0_64, @f
+ $a0_64 = LW64 $sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
+ $t9_64 = LD $gp_64, @g :: (load 8 from call-entry @g)
+ JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ SW killed $v0, $sp_64, 4 :: (store 4 into %ir.retval)
bb.6.return:
- %v0 = LW %sp_64, 4 :: (dereferenceable load 4 from %ir.retval)
- %gp_64 = LD %sp_64, 8 :: (load 8 from %stack.4)
- %fp_64 = LD %sp_64, 16 :: (load 8 from %stack.3)
- %ra_64 = LD %sp_64, 24 :: (load 8 from %stack.2)
- %sp_64 = DADDiu %sp_64, 32
- PseudoReturn64 %ra_64
+ $v0 = LW $sp_64, 4 :: (dereferenceable load 4 from %ir.retval)
+ $gp_64 = LD $sp_64, 8 :: (load 8 from %stack.4)
+ $fp_64 = LD $sp_64, 16 :: (load 8 from %stack.3)
+ $ra_64 = LD $sp_64, 24 :: (load 8 from %stack.2)
+ $sp_64 = DADDiu $sp_64, 32
+ PseudoReturn64 $ra_64
...
diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
index 5bfaef0..83c489d 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
@@ -58,18 +58,18 @@
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$ra' }
body: |
bb.0.entry:
successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)
- liveins: %ra
+ liveins: $ra
- %sp = ADDiu %sp, -24
+ $sp = ADDiu $sp, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed %ra, %sp, 20 :: (store 4 into %stack.0)
- CFI_INSTRUCTION offset %ra_64, -4
- JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0
- BLEZ %v0, %bb.4.if.end, implicit-def %at
+ SW killed $ra, $sp, 20 :: (store 4 into %stack.0)
+ CFI_INSTRUCTION offset $ra_64, -4
+ JAL @k, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def $v0
+ BLEZ $v0, %bb.4.if.end, implicit-def $at
bb.1.if.then:
successors: %bb.2.if.then(0x80000000)
@@ -80,12 +80,12 @@
bb.3.if.then:
successors: %bb.4.if.end(0x80000000)
- %a0 = ADDiu %zero, 2
- JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp
+ $a0 = ADDiu $zero, 2
+ JAL @f, csr_o32_fp64, implicit-def dead $ra, implicit killed $a0, implicit-def $sp
bb.4.if.end:
- %ra = LW %sp, 20 :: (load 4 from %stack.0)
- %sp = ADDiu %sp, 24
- PseudoReturn undef %ra
+ $ra = LW $sp, 20 :: (load 4 from %stack.0)
+ $sp = ADDiu $sp, 24
+ PseudoReturn undef $ra
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
index 8e3b887..d9d7f9a 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXT %0, 55, 10
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
index 968dd4e3..f20677d 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXT %0, 5, 50
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
index bdf82ec..a25f25e 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTM %0, 3, 62
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
index 987a228..3f9c2bd 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTM %0, 65, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
index b1e367e..823519f 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTM %0, 31, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
index 9b6dac0..e62904c 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 43, 30
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
index 65e5bd0..ed0a874 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 64, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
index 8c548f1..f1d0387 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 63, 1
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
index 0511d1a..927862e 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 33, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
index d1d1785..c2f1b89 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINS %0, 17, 17
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
index 1602aa2..6203b87 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINS %0, 55, 10
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
index bf713bf..d69136c 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINS %0, 5, 50
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
index aa73e7f..7cc6c2e 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSM %0, 20, 50
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
index 66a6053..54c55ce 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSM %0, 65, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
index fba3bee..fd18417 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSM %0, 31, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
index 9d2d17c..0153809 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSU %0, 50, 20
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
index d89bb2d..b9b88a9 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSU %0, 65, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
index 550f890..99aee89 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSU %0, 33, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
index 94edecd..c10fe55 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '$a0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0
+ liveins: $a0
- %0 = COPY %a0
+ %0 = COPY $a0
%1 = EXT %0, 17, 17
- %v0 = COPY %1
- RetRA implicit %v0
+ $v0 = COPY %1
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
index 7cca1b6..39a81a6 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '$a0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0
+ liveins: $a0
- %0 = COPY %a0
+ %0 = COPY $a0
%1 = EXT %0, 44, 21
- %v0 = COPY %1
- RetRA implicit %v0
+ $v0 = COPY %1
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
index 4c35e1f..ad6653c 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
@@ -16,7 +16,7 @@
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '$a0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@
constants:
body: |
bb.0.entry:
- liveins: %a0
+ liveins: $a0
- %0 = COPY %a0
+ %0 = COPY $a0
%1 = EXT %0, 0, 33
- %v0 = COPY %1
- RetRA implicit %v0
+ $v0 = COPY %1
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
index e825b59..f8266f0 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
@@ -18,8 +18,8 @@
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%a1', virtual-reg: '%1' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$a1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,13 +42,13 @@
constants:
body: |
bb.0.entry:
- liveins: %a0, %a1
+ liveins: $a0, $a1
- %1 = COPY %a1
- %0 = COPY %a0
+ %1 = COPY $a1
+ %0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 17, 17, %0
- %v0 = COPY %3
- RetRA implicit %v0
+ $v0 = COPY %3
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
index a284fdb..eeac163 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
@@ -18,8 +18,8 @@
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%a1', virtual-reg: '%1' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$a1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,13 +42,13 @@
constants:
body: |
bb.0.entry:
- liveins: %a0, %a1
+ liveins: $a0, $a1
- %1 = COPY %a1
- %0 = COPY %a0
+ %1 = COPY $a1
+ %0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 32, 4, %0
- %v0 = COPY %3
- RetRA implicit %v0
+ $v0 = COPY %3
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
index 6cd839a..6beb781 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
@@ -18,8 +18,8 @@
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%a1', virtual-reg: '%1' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$a1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,13 +42,13 @@
constants:
body: |
bb.0.entry:
- liveins: %a0, %a1
+ liveins: $a0, $a1
- %1 = COPY %a1
- %0 = COPY %a0
+ %1 = COPY $a1
+ %0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 0, 40, %0
- %v0 = COPY %3
- RetRA implicit %v0
+ $v0 = COPY %3
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/call.ll b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
index 2f5349f..d78f1b5 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
@@ -161,8 +161,8 @@
define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
; ALL-LABEL: thunk_undef_double:
-; O32: # implicit-def: %a2
-; O32: # implicit-def: %a3
+; O32: # implicit-def: $a2
+; O32: # implicit-def: $a3
; NOT-R6C: jr $[[TGT]]
; R6C: jrc $[[TGT]]
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
index 6cd0896..53c5910 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
@@ -118,8 +118,8 @@
- { id: 57, class: gpr64, preferred-register: '' }
- { id: 58, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%5' }
- - { reg: '%t9_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '%5' }
+ - { reg: '$t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -143,21 +143,21 @@
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
- liveins: %a0_64, %t9_64
+ liveins: $a0_64, $t9_64
%57 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %58 = DADDu %57, %t9_64
+ %58 = DADDu %57, $t9_64
%6 = DADDiu %58, target-flags(mips-gpoff-lo) @_Z2k1i
- %5 = COPY %a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ %5 = COPY $a0_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%7 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%8 = DADDu killed %7, %6
%9 = LD killed %8, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi)
- %a0_64 = COPY %5
- %gp_64 = COPY %6
- JALR64Pseudo killed %9, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %10 = COPY %v0
+ $a0_64 = COPY %5
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %9, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %10 = COPY $v0
%11 = COPY %5.sub_32
%12 = ADDu %10, killed %11
%13 = LUi64 target-flags(mips-got-hi16) @v
@@ -165,71 +165,71 @@
%15 = LD killed %14, target-flags(mips-got-lo16) @v :: (load 8 from got)
%16 = LW killed %15, 0 :: (dereferenceable load 4 from @v)
%0 = ADDu killed %12, killed %16
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%17 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%18 = DADDu killed %17, %6
%19 = LD killed %18, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%20 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
- %a0_64 = COPY %20
- %gp_64 = COPY %6
- JALR64Pseudo killed %19, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %21 = COPY %v0_64
+ $a0_64 = COPY %20
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %19, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %21 = COPY $v0_64
%22 = DADDiu %21, target-flags(mips-dtprel-hi) @__tls_guard
%23 = LBu killed %22, target-flags(mips-dtprel-lo) @__tls_guard :: (dereferenceable load 1 from @__tls_guard)
- BEQ killed %23, %zero, %bb.2.init.i.i, implicit-def dead %at
- B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at
+ BEQ killed %23, $zero, %bb.2.init.i.i, implicit-def dead $at
+ B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $at
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%39 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%40 = DADDu killed %39, %6
%41 = LD killed %40, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%42 = DADDiu %6, target-flags(mips-tlsgd) @k
- %a0_64 = COPY %42
- %gp_64 = COPY %6
- JALR64Pseudo killed %41, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %43 = COPY %v0_64
+ $a0_64 = COPY %42
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %41, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %43 = COPY $v0_64
%1 = LW %43, 0 :: (dereferenceable load 4 from @k)
- B %bb.3._ZTW1k.exit, implicit-def dead %at
+ B %bb.3._ZTW1k.exit, implicit-def dead $at
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%24 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%25 = DADDu killed %24, %6
%26 = LD %25, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%27 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
- %a0_64 = COPY %27
- %gp_64 = COPY %6
- JALR64Pseudo killed %26, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %28 = COPY %v0_64
+ $a0_64 = COPY %27
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %26, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %28 = COPY $v0_64
%29 = DADDiu %28, target-flags(mips-dtprel-hi) @__tls_guard
- %30 = ADDiu %zero, 1
+ %30 = ADDiu $zero, 1
SB killed %30, killed %29, target-flags(mips-dtprel-lo) @__tls_guard :: (store 1 into @__tls_guard)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%31 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%32 = DADDu killed %31, %6
- %33 = DADDiu %zero_64, 3
+ %33 = DADDiu $zero_64, 3
%34 = LD killed %32, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi)
- %a0_64 = COPY %33
- %gp_64 = COPY %6
- JALR64Pseudo killed %34, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %35 = COPY %v0
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ $a0_64 = COPY %33
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %34, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %35 = COPY $v0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%36 = LD %25, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%37 = DADDiu %6, target-flags(mips-tlsgd) @k
- %a0_64 = COPY %37
- %gp_64 = COPY %6
- JALR64Pseudo killed %36, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %38 = COPY %v0_64
+ $a0_64 = COPY %37
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %36, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %38 = COPY $v0_64
SW %35, %38, 0 :: (store 4 into @k)
%2 = COPY %35
@@ -241,35 +241,35 @@
%44 = LUi64 target-flags(mips-got-hi16) @_ZTH1j
%45 = DADDu killed %44, %6
%46 = LD killed %45, target-flags(mips-got-lo16) @_ZTH1j :: (load 8 from got)
- BEQ64 killed %46, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at
- B %bb.4, implicit-def dead %at
+ BEQ64 killed %46, $zero_64, %bb.5._ZTW1j.exit, implicit-def dead $at
+ B %bb.4, implicit-def dead $at
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%47 = LUi64 target-flags(mips-call-hi16) @_ZTH1j
%48 = DADDu killed %47, %6
%49 = LD killed %48, target-flags(mips-call-lo16) @_ZTH1j :: (load 8 from call-entry @_ZTH1j)
- %gp_64 = COPY %6
- JALR64Pseudo killed %49, csr_n64, implicit-def dead %ra, implicit %gp_64, implicit-def %sp
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %49, csr_n64, implicit-def dead $ra, implicit $gp_64, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
bb.5._ZTW1j.exit:
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%50 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%51 = DADDu killed %50, %6
%52 = LD killed %51, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%53 = DADDiu %6, target-flags(mips-tlsgd) @j
- %a0_64 = COPY %53
- %gp_64 = COPY %6
- JALR64Pseudo killed %52, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %54 = COPY %v0_64
+ $a0_64 = COPY %53
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %52, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %54 = COPY $v0_64
%55 = LW %54, 0 :: (dereferenceable load 4 from @j)
%56 = ADDu %4, killed %55
- %v0 = COPY %56
- RetRA implicit %v0
+ $v0 = COPY %56
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
index 55e520f..a8e1191 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
@@ -45,9 +45,9 @@
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%t9', virtual-reg: '' }
- - { reg: '%v0', virtual-reg: '' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$t9', virtual-reg: '' }
+ - { reg: '$v0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -70,17 +70,17 @@
constants:
body: |
bb.0.entry:
- liveins: %a0, %t9, %v0
+ liveins: $a0, $t9, $v0
- %1 = ADDu %v0, %t9
- %0 = COPY %a0
- ADJCALLSTACKDOWN 16, 0, implicit-def dead %sp, implicit %sp
+ %1 = ADDu $v0, $t9
+ %0 = COPY $a0
+ ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
%2 = LW %1, target-flags(mips-got-call) @_Z1gi :: (load 4 from call-entry @_Z1gi)
- %a0 = COPY %0
- %gp = COPY %1
- JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead %ra, implicit %a0, implicit %gp, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 16, 0, implicit-def dead %sp, implicit %sp
- %3 = COPY %v0
+ $a0 = COPY %0
+ $gp = COPY %1
+ JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
+ %3 = COPY $v0
%4 = ADDu %3, %0
%5 = LW %1, target-flags(mips-got) @v :: (load 4 from got)
%6 = LW killed %5, 0 :: (dereferenceable load 4 from @v)
@@ -88,8 +88,8 @@
%8 = LW %1, target-flags(mips-got) @j :: (load 4 from got)
%9 = LW killed %8, 0 :: (dereferenceable load 4 from @j)
%10 = ADDu killed %7, killed %9
- %v0 = COPY %10
- RetRA implicit %v0
+ $v0 = COPY %10
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
index 2092406..2c3a450 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
@@ -46,8 +46,8 @@
- { id: 12, class: gpr64, preferred-register: '' }
- { id: 13, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
- - { reg: '%t9_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -70,19 +70,19 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64, %t9_64
+ liveins: $a0_64, $t9_64
%12 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %13 = DADDu %12, %t9_64
+ %13 = DADDu %12, $t9_64
%1 = DADDiu %13, target-flags(mips-gpoff-lo) @_Z2k1i
- %0 = COPY %a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ %0 = COPY $a0_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%2 = LD %1, target-flags(mips-got-call) @_Z1gi :: (load 8 from call-entry @_Z1gi)
- %a0_64 = COPY %0
- %gp_64 = COPY %1
- JALR64Pseudo killed %2, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %3 = COPY %v0
+ $a0_64 = COPY %0
+ $gp_64 = COPY %1
+ JALR64Pseudo killed %2, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %3 = COPY $v0
%4 = COPY %0.sub_32
%5 = ADDu %3, killed %4
%6 = LD %1, target-flags(mips-got-disp) @v :: (load 8 from got)
@@ -91,8 +91,8 @@
%9 = LD %1, target-flags(mips-got-disp) @j :: (load 8 from got)
%10 = LW killed %9, 0 :: (dereferenceable load 4 from @j)
%11 = ADDu killed %8, killed %10
- %v0 = COPY %11
- RetRA implicit %v0
+ $v0 = COPY %11
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
index ba0da2f..d088172 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
@@ -110,8 +110,8 @@
- { id: 50, class: gpr64, preferred-register: '' }
- { id: 51, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%5' }
- - { reg: '%t9_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '%5' }
+ - { reg: '$t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -135,18 +135,18 @@
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
- liveins: %a0_64, %t9_64
+ liveins: $a0_64, $t9_64
%50 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %51 = DADDu %50, %t9_64
+ %51 = DADDu %50, $t9_64
%43 = DADDiu %51, target-flags(mips-gpoff-lo) @_Z2k1i
- %5 = COPY %a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ %5 = COPY $a0_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%6 = COPY %5.sub_32
- %a0_64 = COPY %5
- JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %7 = COPY %v0
+ $a0_64 = COPY %5
+ JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %7 = COPY $v0
%8 = ADDu %7, killed %6
%9 = LUi64 target-flags(mips-highest) @v
%10 = DADDiu killed %9, target-flags(mips-higher) @v
@@ -157,46 +157,46 @@
%0 = ADDu killed %8, killed %14
%15 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%16 = DADDiu killed %15, target-flags(mips-tprel-lo) @__tls_guard
- %17 = RDHWR64 %hwr29
- %v1_64 = COPY %17
- %18 = COPY %v1_64
+ %17 = RDHWR64 $hwr29
+ $v1_64 = COPY %17
+ %18 = COPY $v1_64
%19 = DADDu %18, killed %16
%20 = LBu killed %19, 0 :: (dereferenceable load 1 from @__tls_guard)
- BEQ killed %20, %zero, %bb.2.init.i.i, implicit-def dead %at
- J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at
+ BEQ killed %20, $zero, %bb.2.init.i.i, implicit-def dead $at
+ J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $at
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
%32 = LUi64 target-flags(mips-tprel-hi) @k
%33 = DADDiu killed %32, target-flags(mips-tprel-lo) @k
- %34 = RDHWR64 %hwr29
- %v1_64 = COPY %34
- %35 = COPY %v1_64
+ %34 = RDHWR64 $hwr29
+ $v1_64 = COPY %34
+ %35 = COPY $v1_64
%36 = DADDu %35, killed %33
%1 = LW killed %36, 0 :: (dereferenceable load 4 from @k)
- J %bb.3._ZTW1k.exit, implicit-def dead %at
+ J %bb.3._ZTW1k.exit, implicit-def dead $at
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
%21 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%22 = DADDiu killed %21, target-flags(mips-tprel-lo) @__tls_guard
- %23 = RDHWR64 %hwr29
- %v1_64 = COPY %23
- %24 = COPY %v1_64
+ %23 = RDHWR64 $hwr29
+ $v1_64 = COPY %23
+ %24 = COPY $v1_64
%25 = DADDu %24, killed %22
- %26 = ADDiu %zero, 1
+ %26 = ADDiu $zero, 1
SB killed %26, killed %25, 0 :: (store 1 into @__tls_guard)
%27 = LUi64 target-flags(mips-tprel-hi) @k
%28 = DADDiu killed %27, target-flags(mips-tprel-lo) @k
%29 = DADDu %24, killed %28
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- %30 = DADDiu %zero_64, 3
- %a0_64 = COPY %30
- JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %31 = COPY %v0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ %30 = DADDiu $zero_64, 3
+ $a0_64 = COPY %30
+ JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %31 = COPY $v0
SW %31, killed %29, 0 :: (store 4 into @k)
%2 = COPY %31
@@ -211,26 +211,26 @@
%40 = DADDiu killed %39, target-flags(mips-abs-hi) @_ZTH1j
%41 = DSLL killed %40, 16
%42 = DADDiu killed %41, target-flags(mips-abs-lo) @_ZTH1j
- BEQ64 killed %42, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at
- J %bb.4, implicit-def dead %at
+ BEQ64 killed %42, $zero_64, %bb.5._ZTW1j.exit, implicit-def dead $at
+ J %bb.4, implicit-def dead $at
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- JAL @_ZTH1j, csr_n64, implicit-def dead %ra, implicit-def %sp
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ JAL @_ZTH1j, csr_n64, implicit-def dead $ra, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
bb.5._ZTW1j.exit:
- %44 = RDHWR64 %hwr29
- %v1_64 = COPY %44
+ %44 = RDHWR64 $hwr29
+ $v1_64 = COPY %44
%45 = LD %43, target-flags(mips-gottprel) @j :: (load 8)
- %46 = COPY %v1_64
+ %46 = COPY $v1_64
%47 = DADDu %46, killed %45
%48 = LW killed %47, 0 :: (dereferenceable load 4 from @j)
%49 = ADDu %4, killed %48
- %v0 = COPY %49
- RetRA implicit %v0
+ $v0 = COPY %49
+ RetRA implicit $v0
...
diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
index a53368e..c4a8806 100644
--- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
+++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
@@ -77,11 +77,11 @@
tracksRegLiveness: true
registers:
liveins:
- - { reg: '%a0_64', virtual-reg: '' }
- - { reg: '%a1_64', virtual-reg: '' }
- - { reg: '%a2_64', virtual-reg: '' }
- - { reg: '%a3_64', virtual-reg: '' }
- - { reg: '%t0_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$a2_64', virtual-reg: '' }
+ - { reg: '$a3_64', virtual-reg: '' }
+ - { reg: '$t0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -122,91 +122,91 @@
constants:
body: |
bb.0.entry:
- liveins: %a0_64, %a1_64, %a2_64, %a3_64, %t0_64
+ liveins: $a0_64, $a1_64, $a2_64, $a3_64, $t0_64
- SD killed %a0_64, %stack.1.a, 0 :: (store 8 into %ir.1, align 16)
- SD killed %a1_64, %stack.1.a, 8 :: (store 8 into %ir.2)
- %w0 = LD_B %stack.1.a, 0 :: (dereferenceable load 16 from %ir.a)
- SD killed %a2_64, %stack.2.b, 0 :: (store 8 into %ir.4, align 16)
- SD killed %a3_64, %stack.2.b, 8 :: (store 8 into %ir.5)
- %w1 = LD_B %stack.2.b, 0 :: (dereferenceable load 16 from %ir.b)
- ST_B killed %w0, %stack.3.a.addr, 0 :: (store 16 into %ir.a.addr)
- ST_B killed %w1, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
- SW %t0, %stack.5.c.addr, 0, implicit killed %t0_64 :: (store 4 into %ir.c.addr)
- %at_64 = LEA_ADDiu64 %stack.8, 0
- SD killed %at_64, %stack.6.g, 0 :: (store 8 into %ir.g)
- %a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- %a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
- JAL @h, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %a1_64, implicit-def %sp
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %at_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %v0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %v1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t8_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t9_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %ra_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load 16 from %ir.a.addr)
- SD %at_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %v0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %v1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t8_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t9_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %ra_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- %at_64 = LD %stack.7.d, 0 :: (dereferenceable load 8 from %ir.d)
- %v0 = LB %at_64, 0 :: (load 1 from %ir.arrayidx)
- %w1 = FILL_B killed %v0
- %w0 = ADDV_B killed %w0, killed %w1
- %at = LB killed %at_64, 1 :: (load 1 from %ir.arrayidx3)
- %w1 = FILL_B killed %at
- %w0 = ADDV_B killed %w0, killed %w1
- %w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
- %w0 = ADDV_B killed %w1, killed %w0
- ST_B killed %w0, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
- %w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
- ST_B killed %w0, %stack.0.retval, 0 :: (store 16 into %ir.retval)
- %v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load 8 from %ir.20, align 16)
- %v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load 8 from %ir.20 + 8, align 16)
- RetRA implicit %v0_64, implicit %v1_64
+ SD killed $a0_64, %stack.1.a, 0 :: (store 8 into %ir.1, align 16)
+ SD killed $a1_64, %stack.1.a, 8 :: (store 8 into %ir.2)
+ $w0 = LD_B %stack.1.a, 0 :: (dereferenceable load 16 from %ir.a)
+ SD killed $a2_64, %stack.2.b, 0 :: (store 8 into %ir.4, align 16)
+ SD killed $a3_64, %stack.2.b, 8 :: (store 8 into %ir.5)
+ $w1 = LD_B %stack.2.b, 0 :: (dereferenceable load 16 from %ir.b)
+ ST_B killed $w0, %stack.3.a.addr, 0 :: (store 16 into %ir.a.addr)
+ ST_B killed $w1, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
+ SW $t0, %stack.5.c.addr, 0, implicit killed $t0_64 :: (store 4 into %ir.c.addr)
+ $at_64 = LEA_ADDiu64 %stack.8, 0
+ SD killed $at_64, %stack.6.g, 0 :: (store 8 into %ir.g)
+ $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ $a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
+ JAL @h, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $at_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $v0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $v1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t8_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t9_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $ra_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load 16 from %ir.a.addr)
+ SD $at_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $v0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $v1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t8_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t9_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $ra_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ $at_64 = LD %stack.7.d, 0 :: (dereferenceable load 8 from %ir.d)
+ $v0 = LB $at_64, 0 :: (load 1 from %ir.arrayidx)
+ $w1 = FILL_B killed $v0
+ $w0 = ADDV_B killed $w0, killed $w1
+ $at = LB killed $at_64, 1 :: (load 1 from %ir.arrayidx3)
+ $w1 = FILL_B killed $at
+ $w0 = ADDV_B killed $w0, killed $w1
+ $w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
+ $w0 = ADDV_B killed $w1, killed $w0
+ ST_B killed $w0, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
+ $w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
+ ST_B killed $w0, %stack.0.retval, 0 :: (store 16 into %ir.retval)
+ $v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load 8 from %ir.20, align 16)
+ $v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load 8 from %ir.20 + 8, align 16)
+ RetRA implicit $v0_64, implicit $v1_64
...
diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
index 9939fa6..69c9e77 100644
--- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
+++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -17,7 +17,7 @@
tracksRegLiveness: false
registers:
liveins:
- - { reg: '%a0', virtual-reg: '' }
+ - { reg: '$a0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -40,7 +40,7 @@
constants:
body: |
bb.0.entry:
- %zero = SLL_MMR6 killed %zero, 0
- JRC16_MM undef %ra, implicit %v0
+ $zero = SLL_MMR6 killed $zero, 0
+ JRC16_MM undef $ra, implicit $v0
...