Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html
In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.
llvm-svn: 323922
diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
index 523329a..7f22437 100644
--- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
+++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
@@ -46,8 +46,8 @@
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- - { reg: '%x3' }
- - { reg: '%x4' }
+ - { reg: '$x3' }
+ - { reg: '$x4' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -63,36 +63,36 @@
hasVAStart: false
hasMustTailInVarArgFunc: false
fixedStack:
- - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
- - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' }
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
+ - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$x29' }
body: |
bb.0.entry:
- liveins: %x3, %x4, %x29, %x30, %x29, %x30
+ liveins: $x3, $x4, $x29, $x30, $x29, $x30
- %x0 = MFLR8 implicit %lr8
- STD %x0, 16, %x1
- %x1 = STDU %x1, -144, %x1
- STD killed %x29, 120, %x1 :: (store 8 into %fixed-stack.1)
- STD killed %x30, 128, %x1 :: (store 8 into %fixed-stack.0, align 16)
- %x30 = OR8 %x4, %x4
- %x3 = LD 0, killed %x3 :: (load 8 from %ir.p1)
- %x29 = ADDI8 killed %x3, -48
- %x3 = ADDIStocHA %x2, @tasklist_lock
- %x3 = LDtocL @tasklist_lock, killed %x3, implicit %x2 :: (load 8 from got)
- BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def %lr8, implicit %rm, implicit %x3, implicit %x2, implicit-def %r1, implicit-def dead %x3
- %r3 = LI 0
- STW killed %r3, 0, killed %x30 :: (volatile store 4 into %ir.p2)
+ $x0 = MFLR8 implicit $lr8
+ STD $x0, 16, $x1
+ $x1 = STDU $x1, -144, $x1
+ STD killed $x29, 120, $x1 :: (store 8 into %fixed-stack.1)
+ STD killed $x30, 128, $x1 :: (store 8 into %fixed-stack.0, align 16)
+ $x30 = OR8 $x4, $x4
+ $x3 = LD 0, killed $x3 :: (load 8 from %ir.p1)
+ $x29 = ADDI8 killed $x3, -48
+ $x3 = ADDIStocHA $x2, @tasklist_lock
+ $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got)
+ BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ $r3 = LI 0
+ STW killed $r3, 0, killed $x30 :: (volatile store 4 into %ir.p2)
INLINEASM &"#compiler barrier", 25
- INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber %r3, 851977, killed %x29, 12, implicit-def dead early-clobber %cr0
+ INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber $r3, 851977, killed $x29, 12, implicit-def dead early-clobber $cr0
; CHECK-LABEL: @mm_update_next_owner
; CHECK-NOT: lwarx 29, 0, 29
; CHECK-NOT: stwcx. 29, 0, 29
- %cr0 = CMPLWI killed %r3, 0
- %x30 = LD 128, %x1 :: (load 8 from %fixed-stack.0, align 16)
- %x29 = LD 120, %x1 :: (load 8 from %fixed-stack.1)
- %x1 = ADDI8 %x1, 144
- %x0 = LD 16, %x1
- MTLR8 %x0, implicit-def %lr8
- BLR8 implicit %lr8, implicit %rm
+ $cr0 = CMPLWI killed $r3, 0
+ $x30 = LD 128, $x1 :: (load 8 from %fixed-stack.0, align 16)
+ $x29 = LD 120, $x1 :: (load 8 from %fixed-stack.1)
+ $x1 = ADDI8 $x1, 144
+ $x0 = LD 16, $x1
+ MTLR8 $x0, implicit-def $lr8
+ BLR8 implicit $lr8, implicit $rm
...
diff --git a/llvm/test/CodeGen/PowerPC/addegluecrash.ll b/llvm/test/CodeGen/PowerPC/addegluecrash.ll
index 642960f..a1d9805 100644
--- a/llvm/test/CodeGen/PowerPC/addegluecrash.ll
+++ b/llvm/test/CodeGen/PowerPC/addegluecrash.ll
@@ -23,7 +23,7 @@
; CHECK-NEXT: cmpld 7, 4, 5
; CHECK-NEXT: mfocrf 10, 1
; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31
-; CHECK-NEXT: # implicit-def: %x4
+; CHECK-NEXT: # implicit-def: $x4
; CHECK-NEXT: mr 4, 10
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: std 4, 0(3)
diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
index bd0e738..c7ffce2 100644
--- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
+++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
@@ -42,36 +42,36 @@
hasVAStart: false
hasMustTailInVarArgFunc: false
fixedStack:
- - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
- { id: 1, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
body: |
bb.0.entry:
- liveins: %x30, %x30
+ liveins: $x30, $x30
- %x0 = MFLR8 implicit %lr8
- STD %x31, -8, %x1
- STD killed %x0, 16, %x1
- %x1 = STDU %x1, -64, %x1
- %x3 = ADDIStlsldHA %x2, @x
- %x31 = OR8 %x1, %x1
- %x3 = ADDItlsldL killed %x3, @x
- STD killed %x30, 48, %x31 :: (store 8 into %fixed-stack.0, align 16)
- %x3 = GETtlsldADDR killed %x3, @x, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
- %x12 = ADDIStlsgdHA %x2, @y
- %x30 = OR8 killed %x3, %x3
- %x3 = ADDItlsgdL killed %x12, @y
- %x3 = GETtlsADDR killed %x3, @y, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
- %x4 = ADDISdtprelHA killed %x30, @x
+ $x0 = MFLR8 implicit $lr8
+ STD $x31, -8, $x1
+ STD killed $x0, 16, $x1
+ $x1 = STDU $x1, -64, $x1
+ $x3 = ADDIStlsldHA $x2, @x
+ $x31 = OR8 $x1, $x1
+ $x3 = ADDItlsldL killed $x3, @x
+ STD killed $x30, 48, $x31 :: (store 8 into %fixed-stack.0, align 16)
+ $x3 = GETtlsldADDR killed $x3, @x, implicit-def dead $x0, implicit-def dead $x4, implicit-def dead $x5, implicit-def dead $x6, implicit-def dead $x7, implicit-def dead $x8, implicit-def dead $x9, implicit-def dead $x10, implicit-def dead $x11, implicit-def dead $x12, implicit-def $lr8, implicit-def $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead $cr6, implicit-def dead $cr7
+ $x12 = ADDIStlsgdHA $x2, @y
+ $x30 = OR8 killed $x3, $x3
+ $x3 = ADDItlsgdL killed $x12, @y
+ $x3 = GETtlsADDR killed $x3, @y, implicit-def dead $x0, implicit-def dead $x4, implicit-def dead $x5, implicit-def dead $x6, implicit-def dead $x7, implicit-def dead $x8, implicit-def dead $x9, implicit-def dead $x10, implicit-def dead $x11, implicit-def dead $x12, implicit-def $lr8, implicit-def $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead $cr6, implicit-def dead $cr7
+ $x4 = ADDISdtprelHA killed $x30, @x
; CHECK: addis 4, 30, x@dtprel@ha
- %x5 = LI8 1
- %r6 = LI 20
- %x30 = LD 48, %x31 :: (load 8 from %fixed-stack.0, align 16)
- STB8 killed %x5, target-flags(ppc-dtprel-lo) @x, killed %x4 :: (store 1 into @x)
- STW killed %r6, 0, killed %x3 :: (store 4 into @y)
- %x1 = ADDI8 %x1, 64
- %x0 = LD 16, %x1
- %x31 = LD -8, %x1
- MTLR8 killed %x0, implicit-def %lr8
- BLR8 implicit %lr8, implicit %rm
+ $x5 = LI8 1
+ $r6 = LI 20
+ $x30 = LD 48, $x31 :: (load 8 from %fixed-stack.0, align 16)
+ STB8 killed $x5, target-flags(ppc-dtprel-lo) @x, killed $x4 :: (store 1 into @x)
+ STW killed $r6, 0, killed $x3 :: (store 4 into @y)
+ $x1 = ADDI8 $x1, 64
+ $x0 = LD 16, $x1
+ $x31 = LD -8, $x1
+ MTLR8 killed $x0, implicit-def $lr8
+ BLR8 implicit $lr8, implicit $rm
...
diff --git a/llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll b/llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
index c565156..95dd58f 100644
--- a/llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
+++ b/llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
@@ -10,7 +10,7 @@
lnext:
%elementArray = load i32*, i32** %elementArrayPtr, align 8
; CHECK: lwz [[LDREG:[0-9]+]], 124(1) # 4-byte Folded Reload
-; CHECK: # implicit-def: %x[[TEMPREG:[0-9]+]]
+; CHECK: # implicit-def: $x[[TEMPREG:[0-9]+]]
%element = load i32, i32* %elementArray, align 4
; CHECK: mr [[TEMPREG]], [[LDREG]]
; CHECK: clrldi 4, [[TEMPREG]], 32
diff --git a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll
index 6e0b167..ec53dee 100644
--- a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll
+++ b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll
@@ -13,5 +13,5 @@
; Make sure that the MMO on the store has no offset from the byval
; variable itself (we used to have mem:ST8[%v+64]).
-; CHECK: STD killed renamable %x5, 176, %x1; mem:ST8[%v](align=16)
+; CHECK: STD killed renamable $x5, 176, $x1; mem:ST8[%v](align=16)
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir
index 754f838..d5e588d 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir
@@ -94,8 +94,8 @@
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -118,18 +118,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x0, %x4
+ liveins: $x0, $x4
- %1:g8rc = COPY %x4
- %0:g8rc = COPY %x0
+ %1:g8rc = COPY $x4
+ %0:g8rc = COPY $x0
%2:gprc = LI 44
%3:gprc = COPY %1.sub_32
- %4:gprc = ADD4 killed %r0, killed %2
+ %4:gprc = ADD4 killed $r0, killed %2
; CHECK: li 3, 44
; CHECK: add 3, 0, 3
%5:g8rc = EXTSW_32_64 killed %4
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -148,8 +148,8 @@
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -172,18 +172,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x0, %x4
+ liveins: $x0, $x4
- %1:g8rc = COPY %x4
- %0:g8rc = COPY %x0
+ %1:g8rc = COPY $x4
+ %0:g8rc = COPY $x0
%2:gprc = COPY %0.sub_32
%3:gprc = LI 44
- %4:gprc = ADD4 killed %3, killed %r0
+ %4:gprc = ADD4 killed %3, killed $r0
; CHECK: li 3, 44
; CHECK: add 3, 3, 0
%5:g8rc = EXTSW_32_64 killed %4
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -202,8 +202,8 @@
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -226,17 +226,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1:g8rc = COPY %x4
- %0:g8rc = COPY %x3
+ %1:g8rc = COPY $x4
+ %0:g8rc = COPY $x3
%2:gprc = COPY %0.sub_32
- %r0 = LI 44
- %4:gprc = ADD4 killed %r0, killed %2
+ $r0 = LI 44
+ %4:gprc = ADD4 killed $r0, killed %2
; CHECK: addi 3, 3, 44
%5:g8rc = EXTSW_32_64 killed %4
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -255,8 +255,8 @@
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -279,17 +279,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1:g8rc = COPY %x4
- %0:g8rc = COPY %x3
+ %1:g8rc = COPY $x4
+ %0:g8rc = COPY $x3
%2:gprc = COPY %0.sub_32
- %r0 = LI 44
- %4:gprc = ADD4 killed %2, killed %r0
+ $r0 = LI 44
+ %4:gprc = ADD4 killed %2, killed $r0
; CHECK: addi 3, 3, 44
%5:g8rc = EXTSW_32_64 killed %4
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -305,8 +305,8 @@
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x0', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x0', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -329,15 +329,15 @@
constants:
body: |
bb.0.entry:
- liveins: %x0, %x4
+ liveins: $x0, $x4
- %1:g8rc = COPY %x4
+ %1:g8rc = COPY $x4
%0:g8rc_and_g8rc_nox0 = LI8 44
- %2:g8rc = LDX %0, %x0 :: (load 8 from %ir.1, !tbaa !3)
+ %2:g8rc = LDX %0, $x0 :: (load 8 from %ir.1, !tbaa !3)
; CHECK: li 3, 44
; CHECK: ldx 3, 3, 0
- %x3 = COPY %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -353,8 +353,8 @@
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -377,14 +377,14 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1:g8rc = LI8 44
%0:g8rc_and_g8rc_nox0 = LI8 44
- %2:g8rc = LDX %zero8, %1 :: (load 8 from %ir.1, !tbaa !3)
+ %2:g8rc = LDX $zero8, %1 :: (load 8 from %ir.1, !tbaa !3)
; CHECK: ld 3, 44(0)
- %x3 = COPY %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -400,8 +400,8 @@
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -424,13 +424,13 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %x0 = LI8 44
- %0:g8rc_and_g8rc_nox0 = COPY %x3
- %2:g8rc = LDX %0, %x0 :: (load 8 from %ir.1, !tbaa !3)
+ $x0 = LI8 44
+ %0:g8rc_and_g8rc_nox0 = COPY $x3
+ %2:g8rc = LDX %0, $x0 :: (load 8 from %ir.1, !tbaa !3)
; CHECK: ld 3, 44(3)
- %x3 = COPY %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
index 31aa121..7597bc9 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -226,7 +226,7 @@
- { id: 3, class: g8rc, preferred-register: '' }
- { id: 4, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -249,17 +249,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %0 = COPY %x3
+ %0 = COPY $x3
%1 = COPY %0.sub_32
%3 = IMPLICIT_DEF
%2 = LI 170
%4 = RLWNM killed %1, %2, 20, 27
; CHECK: RLWINM killed %1, 10, 20, 27
; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
- %x3 = EXTSW_32_64 %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -276,7 +276,7 @@
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -299,15 +299,15 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
%0 = LI8 234
- %1 = COPY %x3
+ %1 = COPY $x3
%2 = RLWNM8 %1, %0, 20, 27
; CHECK: RLWINM8 %1, 10, 20, 27
; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
- %x3 = COPY %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -331,8 +331,8 @@
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -355,23 +355,23 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI -22
- %4 = RLWNMo %2, %3, 24, 31, implicit-def %cr0
- ; CHECK: RLWINMo %2, 10, 24, 31, implicit-def %cr0
+ %4 = RLWNMo %2, %3, 24, 31, implicit-def $cr0
+ ; CHECK: RLWINMo %2, 10, 24, 31, implicit-def $cr0
; CHECK-LATE: li 3, -22
; CHECK-LATE: rlwinm. 5, 4, 10, 24, 31
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32
- %x3 = COPY %9
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %9
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -394,8 +394,8 @@
- { id: 7, class: crrc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -418,19 +418,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI8 -18
- %3 = RLWNM8o %1, %2, 20, 27, implicit-def %cr0
- ; CHECK: RLWINM8o %1, 14, 20, 27, implicit-def %cr0
+ %3 = RLWNM8o %1, %2, 20, 27, implicit-def $cr0
+ ; CHECK: RLWINM8o %1, 14, 20, 27, implicit-def $cr0
; CHECK-LATE: rlwinm. 3, 4, 14, 20, 27
- %7 = COPY killed %cr0
+ %7 = COPY killed $cr0
%6 = RLDICL killed %3, 0, 32
%8 = ISEL8 %1, %6, %7.sub_eq
- %x3 = COPY %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -453,8 +453,8 @@
- { id: 7, class: g8rc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -477,17 +477,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%5 = LI 210
%8 = SLW killed %2, killed %5
; CHECK: RLWINM killed %2, 18, 0, 13
; CHECK-LATE: slwi 3, 4, 18
- %x3 = EXTSW_32_64 %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -511,8 +511,8 @@
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -535,22 +535,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 35
%3 = COPY %0.sub_32
- %4 = SLWo %3, %2, implicit-def %cr0
- ; CHECK: ANDIo %3, 0, implicit-def %cr0
+ %4 = SLWo %3, %2, implicit-def $cr0
+ ; CHECK: ANDIo %3, 0, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 0
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32
- %x3 = COPY %9
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %9
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -573,8 +573,8 @@
- { id: 7, class: g8rc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -597,17 +597,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 48
%5 = COPY %0.sub_32
%8 = SRW killed %5, killed %2
; CHECK: LI 0
; CHECK-LATE: li 3, 0
- %x3 = EXTSW_32_64 %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -631,8 +631,8 @@
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -655,22 +655,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI -7
%3 = COPY %0.sub_32
- %4 = SRWo %3, %2, implicit-def %cr0
- ; CHECK: ANDIo %3, 0, implicit-def %cr0
+ %4 = SRWo %3, %2, implicit-def $cr0
+ ; CHECK: ANDIo %3, 0, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 0
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32
- %x3 = COPY %9
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %9
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -690,8 +690,8 @@
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -714,19 +714,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 48
%3 = COPY %0.sub_32
- %4 = SRAW killed %3, killed %2, implicit-def dead %carry
+ %4 = SRAW killed %3, killed %2, implicit-def dead $carry
; CHECK: LI 48
- ; CHECK: SRAW killed %3, killed %2, implicit-def dead %carry
+ ; CHECK: SRAW killed %3, killed %2, implicit-def dead $carry
; CHECK-LATE: sraw 3, 3, 4
%5 = EXTSW_32_64 killed %4
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -748,8 +748,8 @@
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -772,20 +772,20 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 80
%3 = COPY %0.sub_32
- %4 = SRAWo killed %3, %2, implicit-def dead %carry, implicit-def %cr0
- ; CHECK: SRAWo killed %3, %2, implicit-def dead %carry, implicit-def %cr0
+ %4 = SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
; CHECK-LATE: sraw. 3, 3, 4
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %4, %5.sub_eq
%7 = EXTSW_32_64 killed %6
- %x3 = COPY %7
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %7
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -804,8 +804,8 @@
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -828,17 +828,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI 140
%4 = RLDCL %0, killed %3, 0
; CHECK: RLDICL %0, 12, 0
; CHECK-LATE: rotldi 3, 3, 12
- %x3 = COPY %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -859,8 +859,8 @@
- { id: 5, class: crrc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -883,19 +883,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = RLDICL %1, 0, 58
%3 = LI -37
- %4 = RLDCLo %0, killed %3, 0, implicit-def %cr0
- ; CHECK: RLDICLo %0, 27, 0, implicit-def %cr0
+ %4 = RLDCLo %0, killed %3, 0, implicit-def $cr0
+ ; CHECK: RLDICLo %0, 27, 0, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 27, 0
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
- %x3 = COPY %6
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %6
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -914,8 +914,8 @@
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -938,17 +938,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI 300
%4 = RLDCR %0, killed %3, 0
; CHECK: RLDICR %0, 44, 0
; CHECK-LATE: rldicr 3, 3, 44, 0
- %x3 = COPY %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -969,8 +969,8 @@
- { id: 5, class: crrc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -993,19 +993,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = RLDICL %1, 0, 58
%3 = LI -18
- %4 = RLDCRo %0, killed %3, 0, implicit-def %cr0
- ; CHECK: RLDICRo %0, 46, 0, implicit-def %cr0
+ %4 = RLDCRo %0, killed %3, 0, implicit-def $cr0
+ ; CHECK: RLDICRo %0, 46, 0, implicit-def $cr0
; CHECK-LATE: rldicr. 5, 3, 46, 0
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
- %x3 = COPY %6
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %6
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1023,8 +1023,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1047,16 +1047,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI -13
%3 = SLD %0, killed %2
; CHECK: LI8 0
; CHECK-LATE: li 3, 0
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1076,8 +1076,8 @@
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1100,18 +1100,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 88
- %3 = SLDo %0, killed %2, implicit-def %cr0
- ; CHECK: ANDIo8 %0, 0, implicit-def %cr0
+ %3 = SLDo %0, killed %2, implicit-def $cr0
+ ; CHECK: ANDIo8 %0, 0, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 0
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = ISEL8 %1, %0, %4.sub_eq
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1129,8 +1129,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1153,16 +1153,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 400
%3 = SRD %0, killed %2
; CHECK: RLDICL %0, 48, 16
; CHECK-LATE: rldicl 3, 3, 48, 16
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1182,8 +1182,8 @@
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1206,18 +1206,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 64
- %3 = SRDo %0, killed %2, implicit-def %cr0
- ; CHECK: ANDIo8 %0, 0, implicit-def %cr0
+ %3 = SRDo %0, killed %2, implicit-def $cr0
+ ; CHECK: ANDIo8 %0, 0, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 0
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = ISEL8 %1, %0, %4.sub_eq
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1235,8 +1235,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1259,16 +1259,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI -44
- %3 = SRAD %0, killed %2, implicit-def dead %carry
- ; CHECK: SRAD %0, killed %2, implicit-def dead %carry
+ %3 = SRAD %0, killed %2, implicit-def dead $carry
+ ; CHECK: SRAD %0, killed %2, implicit-def dead $carry
; CHECK-LATE: srad 3, 3, 4
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1288,8 +1288,8 @@
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1312,18 +1312,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 68
- %3 = SRADo %0, killed %2, implicit-def dead %carry, implicit-def %cr0
- ; CHECK: SRADo %0, killed %2, implicit-def dead %carry, implicit-def %cr0
+ %3 = SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
; CHECK-LATE: srad. 3, 3, 5
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index 408443a..4eb2c39 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -1009,8 +1009,8 @@
- { id: 5, class: gprc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1033,10 +1033,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 33
%3 = COPY %0.sub_32
%4 = ADD4 killed %3, %2
@@ -1046,8 +1046,8 @@
; CHECK-LATE: addi 3, 3, 33
; CHECK-LATE: addi 3, 3, 33
%6 = EXTSW_32_64 killed %5
- %x3 = COPY %6
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %6
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1065,8 +1065,8 @@
- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1089,18 +1089,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1 = LI8 33
- %0 = COPY %x3
+ %0 = COPY $x3
%2 = ADD8 %0, %1
%3 = ADD8 killed %1, killed %2
; CHECK: ADDI8 %0, 33
; CHECK: ADDI8 killed %2, 33
; CHECK-LATE: addi 3, 3, 33
; CHECK-LATE: addi 3, 3, 33
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1123,10 +1123,10 @@
- { id: 7, class: g8rc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
- - { reg: '%x6', virtual-reg: '%3' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
+ - { reg: '$x6', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1149,22 +1149,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5, %x6
+ liveins: $x3, $x4, $x5, $x6
- %3 = COPY %x6
- %2 = COPY %x5
- %1 = COPY %x4
- %0 = COPY %x3
+ %3 = COPY $x6
+ %2 = COPY $x5
+ %1 = COPY $x4
+ %0 = COPY $x3
%4 = COPY %0.sub_32
%5 = LI 55
- %6 = ADDC %5, %4, implicit-def %carry
- ; CHECK: ADDIC %4, 55, implicit-def %carry
+ %6 = ADDC %5, %4, implicit-def $carry
+ ; CHECK: ADDIC %4, 55, implicit-def $carry
; CHECK-LATE: addic 3, 3, 55
- %7 = ADDE8 %3, %1, implicit-def dead %carry, implicit %carry
+ %7 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
%8 = EXTSW_32_64 %6
- %x3 = COPY %8
- %x4 = COPY %7
- BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4
+ $x3 = COPY %8
+ $x4 = COPY %7
+ BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
...
---
@@ -1184,10 +1184,10 @@
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
- - { reg: '%x6', virtual-reg: '%3' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
+ - { reg: '$x6', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1210,19 +1210,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5, %x6
+ liveins: $x3, $x4, $x5, $x6
- %3 = COPY %x6
- %2 = COPY %x5
- %1 = COPY %x4
+ %3 = COPY $x6
+ %2 = COPY $x5
+ %1 = COPY $x4
%0 = LI8 777
- %4 = ADDC8 %2, %0, implicit-def %carry
- ; CHECK: ADDIC8 %2, 777, implicit-def %carry
+ %4 = ADDC8 %2, %0, implicit-def $carry
+ ; CHECK: ADDIC8 %2, 777, implicit-def $carry
; CHECK-LATE: addic 3, 5, 777
- %5 = ADDE8 %3, %1, implicit-def dead %carry, implicit %carry
- %x3 = COPY %4
- %x4 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4
+ %5 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
+ $x3 = COPY %4
+ $x4 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
...
---
@@ -1245,8 +1245,8 @@
- { id: 7, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1269,21 +1269,21 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1 = LI 433
- %0 = COPY %x3
+ %0 = COPY $x3
%2 = COPY %0.sub_32
- %3 = ADDCo %1, %2, implicit-def %cr0, implicit-def %carry
- ; CHECK: ADDICo %2, 433, implicit-def %cr0, implicit-def %carry
+ %3 = ADDCo %1, %2, implicit-def $cr0, implicit-def $carry
+ ; CHECK: ADDICo %2, 433, implicit-def $cr0, implicit-def $carry
; CHECK-LATE: addic. 3, 3, 433
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = COPY %4.sub_eq
%6 = LI8 0
%7 = LI8 -1
%8 = ISEL8 %7, %6, %5
- %x3 = COPY %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1301,7 +1301,7 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1324,16 +1324,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %0 = COPY %x3
+ %0 = COPY $x3
%1 = LI 77
%2 = ADDI killed %1, 44
%3 = EXTSW_32_64 killed %2
; CHECK: LI 121
; CHECK-LATE: li 3, 121
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1351,7 +1351,7 @@
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1374,16 +1374,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %0 = COPY %x3
+ %0 = COPY $x3
%1 = LI8 333
%2 = ADDI8 killed %1, 44
; CHECK: LI8 377
; CHECK-LATE: li 3, 377
%3 = EXTSW killed %2
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1404,8 +1404,8 @@
- { id: 5, class: gprc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1428,19 +1428,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1 = LI 78
- %0 = COPY %x3
+ %0 = COPY $x3
%2 = COPY %0.sub_32
- %3 = ANDo %1, %2, implicit-def %cr0
- ; CHECK: ANDIo %2, 78, implicit-def %cr0
+ %3 = ANDo %1, %2, implicit-def $cr0
+ ; CHECK: ANDIo %2, 78, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 78
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = ISEL %2, %1, %4.sub_eq
%6 = EXTSW_32_64 killed %5
- %x3 = COPY %6
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %6
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1459,8 +1459,8 @@
- { id: 3, class: crrc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1483,17 +1483,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1 = LI8 321
- %0 = COPY %x3
- %2 = AND8o %1, %0, implicit-def %cr0
- ; CHECK: ANDIo8 %0, 321, implicit-def %cr0
+ %0 = COPY $x3
+ %2 = AND8o %1, %0, implicit-def $cr0
+ ; CHECK: ANDIo8 %0, 321, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 321
- %3 = COPY killed %cr0
+ %3 = COPY killed $cr0
%4 = ISEL8 %1, %0, %3.sub_eq
- %x3 = COPY %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1513,8 +1513,8 @@
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1537,17 +1537,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1 = LI8 65533
- %0 = COPY %x3
+ %0 = COPY $x3
%2 = CMPD %0, %1
; CHECK: CMPDI %0, -3
; CHECK-LATE: cmpdi 3, -3
- %4 = ISEL8 %zero8, %0, %2.sub_gt
+ %4 = ISEL8 $zero8, %0, %2.sub_gt
%5 = ADD8 killed %4, %1
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1567,8 +1567,8 @@
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1591,16 +1591,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 89
%2 = CMPDI %0, 87
- %4 = ISEL8 %zero8, %0, %2.sub_gt
+ %4 = ISEL8 $zero8, %0, %2.sub_gt
; CHECK: LI8 0
%5 = ADD8 killed %4, %1
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1620,8 +1620,8 @@
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1644,16 +1644,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 87
%2 = CMPDI %0, 87
- %4 = ISEL8 %zero8, %0, %2.sub_gt
+ %4 = ISEL8 $zero8, %0, %2.sub_gt
; CHECK: COPY %0
%5 = ADD8 killed %4, %1
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1673,8 +1673,8 @@
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1697,17 +1697,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1 = LI8 99
- %0 = COPY %x3
+ %0 = COPY $x3
%2 = CMPLD %0, %1
; CHECK: CMPLDI %0, 99
; CHECK-LATE: cmpldi 3, 99
- %4 = ISEL8 %zero8, %0, %2.sub_gt
+ %4 = ISEL8 $zero8, %0, %2.sub_gt
%5 = ADD8 killed %4, %1
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1727,8 +1727,8 @@
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1751,16 +1751,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 65534
%2 = CMPLDI %0, 65535
- %4 = ISEL8 %zero8, %0, %2.sub_gt
+ %4 = ISEL8 $zero8, %0, %2.sub_gt
; CHECK: COPY %0
%5 = ADD8 killed %4, %1
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1783,8 +1783,8 @@
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1807,19 +1807,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI -1
%3 = COPY %0.sub_32
%4 = CMPW %3, %2
; CHECK: CMPWI %3, -1
- %6 = ISEL %zero, %3, %4.sub_gt
+ %6 = ISEL $zero, %3, %4.sub_gt
%7 = ADD4 killed %6, %2
%8 = EXTSW_32_64 killed %7
- %x3 = COPY %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1842,8 +1842,8 @@
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1866,19 +1866,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI -3
%4 = CMPWI %3, 87
- %6 = ISEL %zero, %3, %4.sub_gt
+ %6 = ISEL $zero, %3, %4.sub_gt
; CHECK: COPY %3
%7 = ADD4 killed %6, killed %2
%8 = EXTSW_32_64 killed %7
- %x3 = COPY %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1903,8 +1903,8 @@
- { id: 9, class: g8rc, preferred-register: '' }
- { id: 10, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1927,22 +1927,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 32767
%3 = COPY %0.sub_32
%4 = CMPLW %3, %2
; CHECK: CMPLWI %3, 32767
; CHECK-LATE: cmplwi 3, 32767
- %6 = ISEL %zero, %3, %4.sub_gt
+ %6 = ISEL $zero, %3, %4.sub_gt
%7 = ADD4 killed %6, %2
%9 = IMPLICIT_DEF
%8 = INSERT_SUBREG %9, killed %7, 1
%10 = RLDICL killed %8, 0, 32
- %x3 = COPY %10
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %10
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -1967,8 +1967,8 @@
- { id: 9, class: g8rc, preferred-register: '' }
- { id: 10, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -1991,21 +1991,21 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI -3
%4 = CMPLWI %3, 87
- %6 = ISEL %zero, %3, %4.sub_gt
+ %6 = ISEL $zero, %3, %4.sub_gt
; CHECK: LI 0
%7 = ADD4 killed %6, killed %2
%9 = IMPLICIT_DEF
%8 = INSERT_SUBREG %9, killed %7, 1
%10 = RLDICL killed %8, 0, 32
- %x3 = COPY %10
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %10
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2037,8 +2037,8 @@
- { id: 16, class: g8rc, preferred-register: '' }
- { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2061,10 +2061,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2082,8 +2082,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLWINM8 killed %14, 0, 24, 31
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2114,8 +2114,8 @@
- { id: 15, class: g8rc, preferred-register: '' }
- { id: 16, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2138,9 +2138,9 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 45
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
@@ -2161,8 +2161,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLWINM8 killed %14, 0, 24, 31
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2194,8 +2194,8 @@
- { id: 16, class: g8rc, preferred-register: '' }
- { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2218,10 +2218,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2239,8 +2239,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLWINM8 killed %14, 0, 16, 31
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2271,8 +2271,8 @@
- { id: 15, class: g8rc, preferred-register: '' }
- { id: 16, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2295,10 +2295,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2316,8 +2316,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLWINM8 killed %14, 0, 16, 31
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2349,8 +2349,8 @@
- { id: 16, class: g8rc, preferred-register: '' }
- { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2373,10 +2373,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2394,8 +2394,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = EXTSH8 killed %14
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2426,8 +2426,8 @@
- { id: 15, class: g8rc, preferred-register: '' }
- { id: 16, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2450,10 +2450,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2473,8 +2473,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = EXTSH8 killed %14
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2507,8 +2507,8 @@
- { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 18, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2531,10 +2531,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2554,8 +2554,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLDICL killed %14, 0, 32
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2586,8 +2586,8 @@
- { id: 15, class: g8rc, preferred-register: '' }
- { id: 16, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2610,9 +2610,9 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 1000
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
@@ -2633,8 +2633,8 @@
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLDICL killed %14, 0, 32
- %x3 = COPY %16
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %16
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2662,8 +2662,8 @@
- { id: 12, class: g8rc, preferred-register: '' }
- { id: 13, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2686,9 +2686,9 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 444
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
@@ -2706,8 +2706,8 @@
; CHECK: LWA 444, killed %11
; CHECK-LATE: lwa 3, 444(4)
%13 = ADD8 killed %12, killed %7
- %x3 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2737,8 +2737,8 @@
- { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 15, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2761,10 +2761,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2781,8 +2781,8 @@
; CHECK: LDU 200, %0
; CHECK-LATE: ldu 4, 200(3)
%13 = ADD8 killed %12, killed %7
- %x3 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2810,8 +2810,8 @@
- { id: 12, class: g8rc, preferred-register: '' }
- { id: 13, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2834,10 +2834,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2854,8 +2854,8 @@
; CHECK: LD 280, %0
; CHECK-LATE: ld 12, 280(3)
%13 = ADD8 killed %12, killed %7
- %x3 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -2885,8 +2885,8 @@
- { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 15, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2909,10 +2909,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -2928,9 +2928,9 @@
%12,%15 = LFDUX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !12)
; CHECK: LFDU 16, %0
; CHECK-LATE: lfdu 1, 16(3)
- %13 = FADD killed %7, killed %12, implicit %rm
- %f1 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %f1
+ %13 = FADD killed %7, killed %12, implicit $rm
+ $f1 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $f1
...
---
@@ -2958,8 +2958,8 @@
- { id: 12, class: f8rc, preferred-register: '' }
- { id: 13, class: f8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -2982,9 +2982,9 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 -20
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
@@ -3001,9 +3001,9 @@
%12 = LFDX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !12)
; CHECK: LFD -20, killed %11
; CHECK-LATE: lfd 1, -20(4)
- %13 = FADD killed %7, killed %12, implicit %rm
- %f1 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %f1
+ %13 = FADD killed %7, killed %12, implicit $rm
+ $f1 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $f1
...
---
@@ -3042,8 +3042,8 @@
- { id: 23, class: g8rc, preferred-register: '' }
- { id: 24, class: vrrc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3081,41 +3081,41 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI8 72
%3, %4 = LFSUX %0, killed %2 :: (load 4 from %ir.arrayidx, !tbaa !14)
; CHECK: LFSU 72, %0
; CHECK-LATE: lfsu 0, 72(3)
- %5 = FCTIWUZ killed %3, implicit %rm
+ %5 = FCTIWUZ killed %3, implicit $rm
%6 = ADDI8 %stack.4, 0
- STFIWX killed %5, %zero8, killed %6
+ STFIWX killed %5, $zero8, killed %6
%7 = LWZ 0, %stack.4 :: (load 4 from %stack.4)
%8 = LFS 4, %4 :: (load 4 from %ir.3, !tbaa !14)
- %10 = FCTIWUZ %8, implicit %rm
+ %10 = FCTIWUZ %8, implicit $rm
%11 = ADDI8 %stack.1, 0
- STFIWX killed %10, %zero8, killed %11
+ STFIWX killed %10, $zero8, killed %11
%12 = LWZ 0, %stack.1 :: (load 4 from %stack.1)
%13 = LFS 8, %4 :: (load 4 from %ir.5, !tbaa !14)
- %15 = FCTIWUZ %13, implicit %rm
+ %15 = FCTIWUZ %13, implicit $rm
%16 = ADDI8 %stack.2, 0
- STFIWX killed %15, %zero8, killed %16
+ STFIWX killed %15, $zero8, killed %16
%17 = LWZ 0, %stack.2 :: (load 4 from %stack.2)
%18 = LFS 12, %4 :: (load 4 from %ir.7, !tbaa !14)
- %20 = FCTIWUZ %18, implicit %rm
+ %20 = FCTIWUZ %18, implicit $rm
%21 = ADDI8 %stack.3, 0
- STFIWX killed %20, %zero8, killed %21
+ STFIWX killed %20, $zero8, killed %21
%22 = LWZ 0, %stack.3 :: (load 4 from %stack.3)
STW killed %7, 0, %stack.0 :: (store 4 into %stack.0, align 16)
STW killed %22, 12, %stack.0 :: (store 4 into %stack.0 + 12)
STW killed %17, 8, %stack.0 :: (store 4 into %stack.0 + 8, align 8)
STW killed %12, 4, %stack.0 :: (store 4 into %stack.0 + 4)
%23 = ADDI8 %stack.0, 0
- %24 = LVX %zero8, killed %23 :: (load 16 from %stack.0)
- %v2 = COPY %24
- BLR8 implicit %lr8, implicit %rm, implicit %v2
+ %24 = LVX $zero8, killed %23 :: (load 16 from %stack.0)
+ $v2 = COPY %24
+ BLR8 implicit $lr8, implicit $rm, implicit $v2
...
---
@@ -3143,8 +3143,8 @@
- { id: 12, class: f4rc, preferred-register: '' }
- { id: 13, class: f4rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3167,10 +3167,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -3186,9 +3186,9 @@
%12 = LFSX %0, killed %11 :: (load 4 from %ir.arrayidx3, !tbaa !14)
; CHECK: LFS -88, %0
; CHECK-LATE: lfs 1, -88(3)
- %13 = FADDS killed %7, killed %12, implicit %rm
- %f1 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %f1
+ %13 = FADDS killed %7, killed %12, implicit $rm
+ $f1 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $f1
...
---
@@ -3216,8 +3216,8 @@
- { id: 12, class: vsfrc, preferred-register: '' }
- { id: 13, class: vsfrc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3240,28 +3240,28 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
%4 = INSERT_SUBREG %5, killed %3, 1
%6 = LI8 100
- %7 = LXSDX %0, killed %6, implicit %rm :: (load 8 from %ir.arrayidx, !tbaa !12)
+ %7 = LXSDX %0, killed %6, implicit $rm :: (load 8 from %ir.arrayidx, !tbaa !12)
; CHECK: LXSD 100, %0
; CHECK-LATE: lxsd 0, 100(3)
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -120
- %12 = LXSDX %0, killed %11, implicit %rm :: (load 8 from %ir.arrayidx3, !tbaa !12)
+ %12 = LXSDX %0, killed %11, implicit $rm :: (load 8 from %ir.arrayidx3, !tbaa !12)
; CHECK: LXSD -120, %0
; CHECK-LATE: lxsd 1, -120(3)
- %13 = XSADDDP killed %7, killed %12, implicit %rm
- %f1 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %f1
+ %13 = XSADDDP killed %7, killed %12, implicit $rm
+ $f1 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $f1
...
---
@@ -3289,8 +3289,8 @@
- { id: 12, class: vssrc, preferred-register: '' }
- { id: 13, class: vssrc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3313,10 +3313,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -3333,8 +3333,8 @@
; CHECK: LXSSP -92, %0
; CHECK-LATE: lxssp 1, -92(3)
%13 = XSADDSP killed %7, killed %12
- %f1 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %f1
+ $f1 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $f1
...
---
@@ -3362,8 +3362,8 @@
- { id: 12, class: vrrc, preferred-register: '' }
- { id: 13, class: vrrc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3386,10 +3386,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
@@ -3406,8 +3406,8 @@
; CHECK: LXV -16, %0
; CHECK-LATE: lxv 35, -16(3)
%13 = VADDUWM killed %12, killed %7
- %v2 = COPY %13
- BLR8 implicit %lr8, implicit %rm, implicit %v2
+ $v2 = COPY %13
+ BLR8 implicit $lr8, implicit $rm, implicit $v2
...
---
@@ -3425,8 +3425,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3449,16 +3449,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI 99
%3 = COPY %1.sub_32
%2 = OR %0, %3
; CHECK: ORI %3, 99
; CHECK-LATE: ori 3, 4, 99
- %x3 = EXTSW_32_64 %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3475,8 +3475,8 @@
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3499,15 +3499,15 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 777
%2 = OR8 %1, %0
; CHECK: ORI8 %1, 777
; CHECK-LATE: ori 3, 4, 777
- %x3 = COPY %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3523,7 +3523,7 @@
- { id: 0, class: gprc, preferred-register: '' }
- { id: 1, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3546,14 +3546,14 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
%0 = LI 777
%1 = ORI %0, 88
; CHECK: LI 857
; CHECK-LATE: li 3, 857
- %x3 = EXTSW_32_64 %1
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %1
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3569,7 +3569,7 @@
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3592,14 +3592,14 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
%0 = LI8 8721
%1 = ORI8 %0, 99
; CHECK: LI8 8819
; CHECK-LATE: li 3, 8819
- %x3 = COPY %1
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %1
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3618,8 +3618,8 @@
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3642,17 +3642,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI 14
%4 = RLDCL %0, killed %3, 0
; CHECK: RLDICL %0, 14, 0
; CHECK-LATE: rotldi 3, 3, 14
- %x3 = COPY %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3673,8 +3673,8 @@
- { id: 5, class: crrc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3697,19 +3697,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = RLDICL %1, 0, 58
%3 = LI 37
- %4 = RLDCLo %0, killed %3, 0, implicit-def %cr0
- ; CHECK: RLDICLo %0, 37, 0, implicit-def %cr0
+ %4 = RLDCLo %0, killed %3, 0, implicit-def $cr0
+ ; CHECK: RLDICLo %0, 37, 0, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 37, 0
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
- %x3 = COPY %6
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %6
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3728,8 +3728,8 @@
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3752,17 +3752,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI 0
%4 = RLDCR %0, killed %3, 0
; CHECK: RLDICR %0, 0, 0
; CHECK-LATE: rldicr 3, 3, 0, 0
- %x3 = COPY %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3783,8 +3783,8 @@
- { id: 5, class: crrc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3807,19 +3807,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = RLDICL %1, 0, 58
%3 = LI 18
- %4 = RLDCRo %0, killed %3, 0, implicit-def %cr0
- ; CHECK: RLDICRo %0, 18, 0, implicit-def %cr0
+ %4 = RLDCRo %0, killed %3, 0, implicit-def $cr0
+ ; CHECK: RLDICRo %0, 18, 0, implicit-def $cr0
; CHECK-LATE: rldicr. 5, 3, 18, 0
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
- %x3 = COPY %6
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %6
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3835,7 +3835,7 @@
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3858,14 +3858,14 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
%0 = LI8 -1
%1 = RLDICL %0, 53, 49
; CHECK: LI8 32767
; CHECK-LATE: li 3, 32767
- %x3 = COPY %1
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %1
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3884,8 +3884,8 @@
- { id: 3, class: crrc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3908,18 +3908,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 -1
- %2 = RLDICLo %0, 53, 48, implicit-def %cr0
+ %2 = RLDICLo %0, 53, 48, implicit-def $cr0
; CHECK: ANDIo8 %0, 65535
; CHECK-LATE: li 3, -1
; CHECK-LATE: andi. 3, 3, 65535
- %3 = COPY killed %cr0
+ %3 = COPY killed $cr0
%4 = ISEL8 %1, %2, %3.sub_eq
- %x3 = COPY %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3938,8 +3938,8 @@
- { id: 3, class: crrc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -3962,17 +3962,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 200
- %2 = RLDICLo %0, 61, 3, implicit-def %cr0
+ %2 = RLDICLo %0, 61, 3, implicit-def $cr0
; CHECK-NOT: ANDI
; CHECK-LATE-NOT: andi.
- %3 = COPY killed %cr0
+ %3 = COPY killed $cr0
%4 = ISEL8 %1, %2, %3.sub_eq
- %x3 = COPY %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -3991,7 +3991,7 @@
- { id: 3, class: g8rc, preferred-register: '' }
- { id: 4, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4014,17 +4014,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %0 = COPY %x3
+ %0 = COPY $x3
%1 = COPY %0.sub_32
%3 = IMPLICIT_DEF
%2 = LI 17
%4 = RLWINM killed %2, 4, 20, 27
; CHECK: LI 272
; CHECK-LATE: li 3, 272
- %x3 = EXTSW_32_64 %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4043,7 +4043,7 @@
- { id: 3, class: g8rc, preferred-register: '' }
- { id: 4, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4066,17 +4066,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %0 = COPY %x3
+ %0 = COPY $x3
%1 = COPY %0.sub_32
%3 = IMPLICIT_DEF
%2 = LI 2
%4 = RLWINM killed %2, 31, 0, 31
; CHECK: LI 1
; CHECK-LATE: li 3, 1
- %x3 = EXTSW_32_64 %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4095,7 +4095,7 @@
- { id: 3, class: g8rc, preferred-register: '' }
- { id: 4, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4118,17 +4118,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %0 = COPY %x3
+ %0 = COPY $x3
%1 = COPY %0.sub_32
%3 = IMPLICIT_DEF
%2 = LI 1
%4 = RLWINM killed %2, 31, 0, 31
; CHECK: RLWINM killed %2, 31, 0, 31
; CHECK-LATE: rotlwi 3, 3, 31
- %x3 = EXTSW_32_64 %4
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %4
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4144,7 +4144,7 @@
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4167,14 +4167,14 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
%0 = LI8 234
%1 = RLWINM8 %0, 4, 20, 27
; CHECK: LI8 3744
; CHECK-LATE: li 3, 3744
- %x3 = COPY %1
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %1
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4198,8 +4198,8 @@
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4222,23 +4222,23 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI -22
- %4 = RLWINMo %3, 0, 24, 31, implicit-def %cr0
+ %4 = RLWINMo %3, 0, 24, 31, implicit-def $cr0
; CHECK: ANDIo %3, 234
; CHECK-LATE: li 3, -22
; CHECK-LATE: andi. 5, 3, 234
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32
- %x3 = COPY %9
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %9
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4262,8 +4262,8 @@
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4286,22 +4286,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI -22
- %4 = RLWINMo %3, 5, 24, 31, implicit-def %cr0
+ %4 = RLWINMo %3, 5, 24, 31, implicit-def $cr0
; CHECK-NOT: ANDI
; CHECK-LATE-NOT: andi.
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32
- %x3 = COPY %9
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %9
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4324,8 +4324,8 @@
- { id: 7, class: crrc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4348,20 +4348,20 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI8 -18
- %3 = RLWINM8o %2, 4, 20, 27, implicit-def %cr0
+ %3 = RLWINM8o %2, 4, 20, 27, implicit-def $cr0
; CHECK: ANDIo8 %2, 3808
; CHECK-LATE: li 3, -18
; CHECK-LATE: andi. 3, 3, 3808
- %7 = COPY killed %cr0
+ %7 = COPY killed $cr0
%6 = RLDICL killed %3, 0, 32
%8 = ISEL8 %1, %6, %7.sub_eq
- %x3 = COPY %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4379,8 +4379,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4403,16 +4403,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 13
%3 = SLD %0, killed %2
; CHECK: RLDICR %0, 13, 50
; CHECK-LATE: sldi 3, 3, 13
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4432,8 +4432,8 @@
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4456,18 +4456,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 17
- %3 = SLDo %0, killed %2, implicit-def %cr0
- ; CHECK: RLDICRo %0, 17, 46, implicit-def %cr0
+ %3 = SLDo %0, killed %2, implicit-def $cr0
+ ; CHECK: RLDICRo %0, 17, 46, implicit-def $cr0
; CHECK-LATE: rldicr. 5, 3, 17, 46
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = ISEL8 %1, %0, %4.sub_eq
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4485,8 +4485,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4509,16 +4509,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 4
%3 = SRD %0, killed %2
; CHECK: RLDICL %0, 60, 4
; CHECK-LATE: rldicl 3, 3, 60, 4
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4538,8 +4538,8 @@
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4562,18 +4562,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 17
- %3 = SRDo %0, killed %2, implicit-def %cr0
- ; CHECK: RLDICLo %0, 47, 17, implicit-def %cr0
+ %3 = SRDo %0, killed %2, implicit-def $cr0
+ ; CHECK: RLDICLo %0, 47, 17, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 47, 17
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = ISEL8 %1, %0, %4.sub_eq
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4596,8 +4596,8 @@
- { id: 7, class: g8rc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4620,17 +4620,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = COPY %1.sub_32
%5 = LI 21
%8 = SLW killed %2, killed %5
; CHECK: RLWINM killed %2, 21, 0, 10
; CHECK-LATE: slwi 3, 4, 21
- %x3 = EXTSW_32_64 %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4654,8 +4654,8 @@
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4678,22 +4678,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 11
%3 = COPY %0.sub_32
- %4 = SLWo %3, %2, implicit-def %cr0
- ; CHECK: RLWINMo %3, 11, 0, 20, implicit-def %cr0
+ %4 = SLWo %3, %2, implicit-def $cr0
+ ; CHECK: RLWINMo %3, 11, 0, 20, implicit-def $cr0
; CHECK-LATE: rlwinm. 5, 3, 11, 0, 20
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32
- %x3 = COPY %9
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %9
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4716,8 +4716,8 @@
- { id: 7, class: g8rc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4740,17 +4740,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 8
%5 = COPY %0.sub_32
%8 = SRW killed %5, killed %2
; CHECK: RLWINM killed %5, 24, 8, 31
; CHECK-LATE: srwi 3, 3, 8
- %x3 = EXTSW_32_64 %8
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4774,8 +4774,8 @@
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4798,22 +4798,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 7
%3 = COPY %0.sub_32
- %4 = SRWo %3, %2, implicit-def %cr0
+ %4 = SRWo %3, %2, implicit-def $cr0
; CHECK: RLWINMo %3, 25, 7, 31
; CHECK-LATE: rlwinm. 5, 3, 25, 7, 31
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32
- %x3 = COPY %9
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %9
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4833,8 +4833,8 @@
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4857,18 +4857,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 15
%3 = COPY %0.sub_32
- %4 = SRAW killed %3, killed %2, implicit-def dead %carry
- ; CHECK: SRAWI killed %3, 15, implicit-def dead %carry
+ %4 = SRAW killed %3, killed %2, implicit-def dead $carry
+ ; CHECK: SRAWI killed %3, 15, implicit-def dead $carry
; CHECK-LATE: srawi 3, 3, 15
%5 = EXTSW_32_64 killed %4
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4890,8 +4890,8 @@
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4914,20 +4914,20 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 8
%3 = COPY %0.sub_32
- %4 = SRAWo killed %3, %2, implicit-def dead %carry, implicit-def %cr0
- ; CHECK: SRAWIo killed %3, 8, implicit-def dead %carry, implicit-def %cr0
+ %4 = SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRAWIo killed %3, 8, implicit-def dead $carry, implicit-def $cr0
; CHECK-LATE: srawi. 3, 3, 8
- %5 = COPY killed %cr0
+ %5 = COPY killed $cr0
%6 = ISEL %2, %4, %5.sub_eq
%7 = EXTSW_32_64 killed %6
- %x3 = COPY %7
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %7
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4945,8 +4945,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -4969,16 +4969,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 44
- %3 = SRAD %0, killed %2, implicit-def dead %carry
- ; CHECK: SRADI %0, 44, implicit-def dead %carry
+ %3 = SRAD %0, killed %2, implicit-def dead $carry
+ ; CHECK: SRADI %0, 44, implicit-def dead $carry
; CHECK-LATE: sradi 3, 3, 44
- %x3 = COPY %3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -4998,8 +4998,8 @@
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5022,18 +5022,18 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
- %0 = COPY %x3
+ %1 = COPY $x4
+ %0 = COPY $x3
%2 = LI 61
- %3 = SRADo %0, killed %2, implicit-def dead %carry, implicit-def %cr0
- ; CHECK: SRADIo %0, 61, implicit-def dead %carry, implicit-def %cr0
+ %3 = SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRADIo %0, 61, implicit-def dead $carry, implicit-def $cr0
; CHECK-LATE: sradi. 3, 3, 61
- %4 = COPY killed %cr0
+ %4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
- %x3 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -5062,9 +5062,9 @@
- { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5087,11 +5087,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $x4
+ %0 = COPY $x3
%3 = COPY %1.sub_32
%4 = COPY %2.sub_32
%5 = ADDI %4, 1
@@ -5108,7 +5108,7 @@
%14 = STBUX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3)
; CHECK: STBU %3, 777, %0
; CHECK-LATE: 4, 777(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5135,9 +5135,9 @@
- { id: 11, class: g8rc, preferred-register: '' }
- { id: 12, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5160,10 +5160,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
+ %2 = COPY $x5
+ %1 = COPY $x4
%0 = LI8 975
%3 = COPY %1.sub_32
%4 = COPY %2.sub_32
@@ -5181,7 +5181,7 @@
STBX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3)
; CHECK: STB %3, 975, killed %12
; CHECK-LATE: stb 4, 975(5)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5210,9 +5210,9 @@
- { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5235,11 +5235,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $x4
+ %0 = COPY $x3
%3 = COPY %1.sub_32
%4 = COPY %2.sub_32
%5 = ADDI %4, 1
@@ -5256,7 +5256,7 @@
%14 = STHUX %3, %0, killed %12 :: (store 2 into %ir.arrayidx3, !tbaa !6)
; CHECK: STHU %3, -761, %0
; CHECK-LATE: sthu 4, -761(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5283,9 +5283,9 @@
- { id: 11, class: g8rc, preferred-register: '' }
- { id: 12, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5308,11 +5308,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $x4
+ %0 = COPY $x3
%3 = COPY %1.sub_32
%4 = COPY %2.sub_32
%5 = ADDI %4, 1
@@ -5329,7 +5329,7 @@
STHX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3)
; CHECK: STH %3, -900, %0
; CHECK-LATE: sth 4, -900(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5358,9 +5358,9 @@
- { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5383,11 +5383,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $x4
+ %0 = COPY $x3
%3 = COPY %1.sub_32
%4 = COPY %2.sub_32
%5 = ADDI %4, 1
@@ -5404,7 +5404,7 @@
%14 = STWUX %3, %0, killed %12 :: (store 4 into %ir.arrayidx3, !tbaa !8)
; CHECK: STWU %3, 0, %0
; CHECK-LATE: stwu 4, 0(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5431,9 +5431,9 @@
- { id: 11, class: g8rc, preferred-register: '' }
- { id: 12, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5456,11 +5456,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $x4
+ %0 = COPY $x3
%3 = COPY %1.sub_32
%4 = COPY %2.sub_32
%5 = ADDI %4, 1
@@ -5477,7 +5477,7 @@
STWX %3, %0, killed %12 :: (store 4 into %ir.arrayidx3, !tbaa !8)
; CHECK: STW %3, 99, %0
; CHECK-LATE: stw 4, 99(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5505,9 +5505,9 @@
- { id: 12, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5530,11 +5530,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $x4
+ %0 = COPY $x3
%3 = COPY %2.sub_32
%4 = ADDI %3, 1
%6 = IMPLICIT_DEF
@@ -5550,7 +5550,7 @@
%13 = STDUX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !10)
; CHECK: STDU %1, -8, %0
; CHECK-LATE: stdu 4, -8(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5576,9 +5576,9 @@
- { id: 10, class: g8rc, preferred-register: '' }
- { id: 11, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5601,10 +5601,10 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %2 = COPY %x5
- %1 = COPY %x4
+ %2 = COPY $x5
+ %1 = COPY $x4
%0 = LI8 1000
%3 = COPY %2.sub_32
%4 = ADDI %3, 1
@@ -5621,7 +5621,7 @@
STDX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !10)
; CHECK: STD %1, 1000, killed %11
; CHECK-LATE: 4, 1000(6)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5647,9 +5647,9 @@
- { id: 10, class: g8rc, preferred-register: '' }
- { id: 11, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%f1', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$f1', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5672,11 +5672,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %f1, %x5
+ liveins: $x3, $f1, $x5
- %2 = COPY %x5
- %1 = COPY %f1
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $f1
+ %0 = COPY $x3
%3 = COPY %2.sub_32
%4 = ADDI %3, 1
%6 = IMPLICIT_DEF
@@ -5692,7 +5692,7 @@
STFSX %1, %0, killed %11 :: (store 4 into %ir.arrayidx3, !tbaa !14)
; CHECK: STFS %1, -401, %0
; CHECK-LATE: stfs 1, -401(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5720,9 +5720,9 @@
- { id: 12, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%f1', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$f1', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5745,11 +5745,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %f1, %x5
+ liveins: $x3, $f1, $x5
- %2 = COPY %x5
- %1 = COPY %f1
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $f1
+ %0 = COPY $x3
%3 = COPY %2.sub_32
%4 = ADDI %3, 1
%6 = IMPLICIT_DEF
@@ -5765,7 +5765,7 @@
%13 = STFSUX %1, %0, killed %11 :: (store 4 into %ir.arrayidx3, !tbaa !14)
; CHECK: STFSU %1, 987, %0
; CHECK-LATE: stfsu 1, 987(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5791,9 +5791,9 @@
- { id: 10, class: g8rc, preferred-register: '' }
- { id: 11, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%f1', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$f1', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5816,11 +5816,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %f1, %x5
+ liveins: $x3, $f1, $x5
- %2 = COPY %x5
- %1 = COPY %f1
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $f1
+ %0 = COPY $x3
%3 = COPY %2.sub_32
%4 = ADDI %3, 1
%6 = IMPLICIT_DEF
@@ -5836,7 +5836,7 @@
STFDX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !12)
; CHECK: STFD %1, -873, %0
; CHECK-LATE: stfd 1, -873(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5864,9 +5864,9 @@
- { id: 12, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%f1', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$f1', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5889,11 +5889,11 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %f1, %x5
+ liveins: $x3, $f1, $x5
- %2 = COPY %x5
- %1 = COPY %f1
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $f1
+ %0 = COPY $x3
%3 = COPY %2.sub_32
%4 = ADDI %3, 1
%6 = IMPLICIT_DEF
@@ -5909,7 +5909,7 @@
%13 = STFDUX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !12)
; CHECK: STFDU %1, 6477, %0
; CHECK-LATE: stfdu 1, 6477(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5927,9 +5927,9 @@
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%f1', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$f1', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -5952,16 +5952,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %f1, %x5
+ liveins: $x3, $f1, $x5
- %2 = COPY %x5
- %1 = COPY %f1
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $f1
+ %0 = COPY $x3
%3 = LI8 444
STXSSPX %1, %0, killed %3 :: (store 4 into %ir.arrayidx, !tbaa !14)
; CHECK: STXSSP %1, 444, %0
; CHECK-LATE: stxssp 1, 444(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -5979,9 +5979,9 @@
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%f1', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$f1', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6004,16 +6004,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %f1, %x5
+ liveins: $x3, $f1, $x5
- %2 = COPY %x5
- %1 = COPY %f1
- %0 = COPY %x3
+ %2 = COPY $x5
+ %1 = COPY $f1
+ %0 = COPY $x3
%3 = LI8 4
- STXSDX %1, %0, killed %3, implicit %rm :: (store 8 into %ir.arrayidx, !tbaa !12)
+ STXSDX %1, %0, killed %3, implicit $rm :: (store 8 into %ir.arrayidx, !tbaa !12)
; CHECK: STXSD %1, 4, %0
; CHECK-LATE: stxsd 1, 4(3)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -6031,9 +6031,9 @@
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%v2', virtual-reg: '%1' }
- - { reg: '%x7', virtual-reg: '%2' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$v2', virtual-reg: '%1' }
+ - { reg: '$x7', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6056,16 +6056,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %v2, %x7
+ liveins: $x3, $v2, $x7
- %2 = COPY %x7
- %1 = COPY %v2
+ %2 = COPY $x7
+ %1 = COPY $v2
%0 = LI8 16
%3 = RLDICR %2, 4, 59
STXVX %1, %0, killed %3 :: (store 16 into %ir.arrayidx, !tbaa !3)
; CHECK: STXV %1, 16, killed %3
; CHECK-LATE: stxv 34, 16(4)
- BLR8 implicit %lr8, implicit %rm
+ BLR8 implicit $lr8, implicit $rm
...
---
@@ -6088,10 +6088,10 @@
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
- - { reg: '%x6', virtual-reg: '%3' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
+ - { reg: '$x6', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6114,22 +6114,22 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5, %x6
+ liveins: $x3, $x4, $x5, $x6
- %3 = COPY %x6
- %2 = COPY %x5
- %1 = COPY %x4
+ %3 = COPY $x6
+ %2 = COPY $x5
+ %1 = COPY $x4
%6 = COPY %3.sub_32
%7 = COPY %2.sub_32
%8 = COPY %1.sub_32
%0 = LI 55
- %4 = SUBFC %7, %0, implicit-def %carry
+ %4 = SUBFC %7, %0, implicit-def $carry
; CHECK: SUBFIC %7, 55
; CHECK-LATE: subfic 3, 5, 55
- %5 = SUBFE %6, %8, implicit-def dead %carry, implicit %carry
- %x3 = EXTSW_32_64 %4
- %x4 = EXTSW_32_64 %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4
+ %5 = SUBFE %6, %8, implicit-def dead $carry, implicit $carry
+ $x3 = EXTSW_32_64 %4
+ $x4 = EXTSW_32_64 %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
...
---
@@ -6149,10 +6149,10 @@
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
- - { reg: '%x5', virtual-reg: '%2' }
- - { reg: '%x6', virtual-reg: '%3' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
+ - { reg: '$x5', virtual-reg: '%2' }
+ - { reg: '$x6', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6175,19 +6175,19 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5, %x6
+ liveins: $x3, $x4, $x5, $x6
- %3 = COPY %x6
- %2 = COPY %x5
- %1 = COPY %x4
+ %3 = COPY $x6
+ %2 = COPY $x5
+ %1 = COPY $x4
%0 = LI8 7635
- %4 = SUBFC8 %2, %0, implicit-def %carry
+ %4 = SUBFC8 %2, %0, implicit-def $carry
; CHECK: SUBFIC8 %2, 7635
; CHECK-LATE: subfic 3, 5, 7635
- %5 = SUBFE8 %3, %1, implicit-def dead %carry, implicit %carry
- %x3 = COPY %4
- %x4 = COPY %5
- BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4
+ %5 = SUBFE8 %3, %1, implicit-def dead $carry, implicit $carry
+ $x3 = COPY %4
+ $x4 = COPY %5
+ BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
...
---
@@ -6205,8 +6205,8 @@
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6229,16 +6229,16 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
%1 = LI 10101
- %0 = COPY %x3
+ %0 = COPY $x3
%3 = COPY %0.sub_32
%2 = XOR %1, %3
; CHECK: XORI %3, 10101
; CHECK-LATE: 3, 3, 10101
- %x3 = EXTSW_32_64 %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -6255,8 +6255,8 @@
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
- - { reg: '%x4', virtual-reg: '%1' }
+ - { reg: '$x3', virtual-reg: '%0' }
+ - { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6279,15 +6279,15 @@
constants:
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %1 = COPY %x4
+ %1 = COPY $x4
%0 = LI8 5535
%2 = XOR8 %1, %0
; CHECK: XORI8 %1, 5535
; CHECK-LATE: xori 3, 4, 5535
- %x3 = COPY %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -6303,7 +6303,7 @@
- { id: 0, class: gprc, preferred-register: '' }
- { id: 1, class: gprc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6326,14 +6326,14 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
%0 = LI 871
%1 = XORI %0, 17
; CHECK: LI 886
; CHECK-LATE: li 3, 886
- %x3 = EXTSW_32_64 %1
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = EXTSW_32_64 %1
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
@@ -6349,7 +6349,7 @@
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -6372,13 +6372,13 @@
constants:
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
%0 = LI8 453
%1 = XORI8 %0, 17
; CHECK: LI8 468
; CHECK-LATE: li 3, 468
- %x3 = COPY %1
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %1
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
diff --git a/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll b/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll
index e6f0ee2..220ae92 100644
--- a/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll
+++ b/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll
@@ -26,10 +26,10 @@
; CHECK: [[DL:![0-9]+]] = !DILocalVariable(name: "result"
;
; High 32 bits in R3, low 32 bits in R4
-; CHECK: %0:gprc = COPY %r3
-; CHECK: DBG_VALUE debug-use %0, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; CHECK: %1:gprc = COPY %r4
-; CHECK: DBG_VALUE debug-use %1, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32)
+; CHECK: %0:gprc = COPY $r3
+; CHECK: DBG_VALUE debug-use %0, debug-use $noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32)
+; CHECK: %1:gprc = COPY $r4
+; CHECK: DBG_VALUE debug-use %1, debug-use $noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32)
define void @bar() local_unnamed_addr #0 !dbg !6 {
%1 = alloca i64, align 8
%2 = tail call i64 @foo()
diff --git a/llvm/test/CodeGen/PowerPC/debuginfo-stackarg.ll b/llvm/test/CodeGen/PowerPC/debuginfo-stackarg.ll
index 1db55dc..8ea6ce8 100644
--- a/llvm/test/CodeGen/PowerPC/debuginfo-stackarg.ll
+++ b/llvm/test/CodeGen/PowerPC/debuginfo-stackarg.ll
@@ -33,7 +33,7 @@
; We expect to find a DBG_VALUE refering to the metadata id for bar5, using the lowest
; of the two fixed stack offsets found earlier.
; CHECK-LABEL: body:
-; CHECK: DBG_VALUE %r1, 0, !17, !DIExpression(DW_OP_plus_uconst, 56)
+; CHECK: DBG_VALUE $r1, 0, !17, !DIExpression(DW_OP_plus_uconst, 56)
entry:
tail call void @llvm.dbg.value(metadata i64 %bar1, metadata !13, metadata !DIExpression()), !dbg !18
tail call void @llvm.dbg.value(metadata i64 %bar2, metadata !14, metadata !DIExpression()), !dbg !19
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-1.mir b/llvm/test/CodeGen/PowerPC/expand-isel-1.mir
index e666ad4..9577aed 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-1.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-1.mir
@@ -22,8 +22,8 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x0' }
- - { reg: '%x3' }
+ - { reg: '$x0' }
+ - { reg: '$x3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -40,18 +40,18 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x0, %x3
+ liveins: $x0, $x3
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r0 = ISEL %zero, %r0, %cr0gt
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r0 = ISEL $zero, $r0, $cr0gt
; CHECK-LABEL: testExpandISEL
- ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+ ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK-NEXT: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r0 = ADDI %zero, 0
+ ; CHECK: $r0 = ADDI $zero, 0
- %x3 = EXTSW_32_64 %r0
+ $x3 = EXTSW_32_64 $r0
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-10.mir b/llvm/test/CodeGen/PowerPC/expand-isel-10.mir
index 017b512..5f7e2a1 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-10.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-10.mir
@@ -23,7 +23,7 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x3' }
+ - { reg: '$x3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -40,15 +40,15 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r3 = ISEL %r3, %r3, %cr0gt
- %x3 = EXTSW_32_64 %r3
- ; CHECK: %r5 = ADDI %r3, 1
- ; CHECK: %cr0 = CMPWI %r3, 0
- ; CHECK-NOT: %r3 = ISEL %r3, %r3, %cr0gt
- ; CHECK: %x3 = EXTSW_32_64 %r3
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r3 = ISEL $r3, $r3, $cr0gt
+ $x3 = EXTSW_32_64 $r3
+ ; CHECK: $r5 = ADDI $r3, 1
+ ; CHECK: $cr0 = CMPWI $r3, 0
+ ; CHECK-NOT: $r3 = ISEL $r3, $r3, $cr0gt
+ ; CHECK: $x3 = EXTSW_32_64 $r3
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-2.mir b/llvm/test/CodeGen/PowerPC/expand-isel-2.mir
index 8e9c3a2..2ad3a84 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-2.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-2.mir
@@ -22,9 +22,9 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x0' }
- - { reg: '%x3' }
- - { reg: '%x4' }
+ - { reg: '$x0' }
+ - { reg: '$x3' }
+ - { reg: '$x4' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -41,17 +41,17 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x0, %x3, %x4
+ liveins: $x0, $x3, $x4
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r3 = ISEL %zero, %r4, %cr0gt
- ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r3 = ISEL $zero, $r4, $cr0gt
+ ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK: %[[FALSE:bb.[0-9]+]]
- ; CHECK: %r3 = ORI %r4, 0
+ ; CHECK: $r3 = ORI $r4, 0
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r3 = ADDI %zero, 0
+ ; CHECK: $r3 = ADDI $zero, 0
- %x3 = EXTSW_32_64 %r3
+ $x3 = EXTSW_32_64 $r3
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-3.mir b/llvm/test/CodeGen/PowerPC/expand-isel-3.mir
index c898726..924ac19 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-3.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-3.mir
@@ -22,9 +22,9 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x0' }
- - { reg: '%x3' }
- - { reg: '%x4' }
+ - { reg: '$x0' }
+ - { reg: '$x3' }
+ - { reg: '$x4' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -41,18 +41,18 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x0, %x3, %x4
+ liveins: $x0, $x3, $x4
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r3 = ISEL %r4, %r0, %cr0gt
- ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r3 = ISEL $r4, $r0, $cr0gt
+ ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK: %[[FALSE:bb.[0-9]+]]
- ; CHECK: %r3 = ORI %r0, 0
+ ; CHECK: $r3 = ORI $r0, 0
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r3 = ADDI %r4, 0
+ ; CHECK: $r3 = ADDI $r4, 0
- %x3 = EXTSW_32_64 %r3
+ $x3 = EXTSW_32_64 $r3
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-4.mir b/llvm/test/CodeGen/PowerPC/expand-isel-4.mir
index 83624f7..e552bc1 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-4.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-4.mir
@@ -1,5 +1,5 @@
# This file tests the scenario: ISEL R0, ZERO, RX, CR (X != 0)
-# It also tests redundant liveins (%x7) and killed registers.
+# It also tests redundant liveins ($x7) and killed registers.
# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
--- |
@@ -23,9 +23,9 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x0' }
- - { reg: '%x3' }
- - { reg: '%x7' }
+ - { reg: '$x0' }
+ - { reg: '$x3' }
+ - { reg: '$x7' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,18 +42,18 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x0, %x3, %x7
+ liveins: $x0, $x3, $x7
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r0 = ISEL killed %zero, killed %r5, killed %cr0gt, implicit killed %cr0
- ; CHECK: BC killed %cr0gt, %[[TRUE:bb.[0-9]+]]
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r0 = ISEL killed $zero, killed $r5, killed $cr0gt, implicit killed $cr0
+ ; CHECK: BC killed $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK: %[[FALSE:bb.[0-9]+]]
- ; CHECK: %r0 = ORI killed %r5, 0
+ ; CHECK: $r0 = ORI killed $r5, 0
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r0 = ADDI killed %zero, 0
+ ; CHECK: $r0 = ADDI killed $zero, 0
- %x0 = EXTSW_32_64 killed %r0
+ $x0 = EXTSW_32_64 killed $r0
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-5.mir b/llvm/test/CodeGen/PowerPC/expand-isel-5.mir
index 7a7130f..352d5e0 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-5.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-5.mir
@@ -22,8 +22,8 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x0' }
- - { reg: '%x3' }
+ - { reg: '$x0' }
+ - { reg: '$x3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -40,15 +40,15 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x0, %x3
+ liveins: $x0, $x3
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r0 = ISEL %r5, %r0, %cr0gt
- ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r0 = ISEL $r5, $r0, $cr0gt
+ ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r0 = ADDI %r5, 0
- %x3 = EXTSW_32_64 %r0
+ ; CHECK: $r0 = ADDI $r5, 0
+ $x3 = EXTSW_32_64 $r0
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-6.mir b/llvm/test/CodeGen/PowerPC/expand-isel-6.mir
index 5aed399..e0fe66e 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-6.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-6.mir
@@ -23,8 +23,8 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x0' }
- - { reg: '%x3' }
+ - { reg: '$x0' }
+ - { reg: '$x3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -41,17 +41,17 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x0, %x3
+ liveins: $x0, $x3
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r3 = ISEL %zero, %r0, %cr0gt
- ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r3 = ISEL $zero, $r0, $cr0gt
+ ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK: %[[FALSE:bb.[0-9]+]]
- ; CHECK: %r3 = ORI %r0, 0
+ ; CHECK: $r3 = ORI $r0, 0
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r3 = ADDI %zero, 0
+ ; CHECK: $r3 = ADDI $zero, 0
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-7.mir b/llvm/test/CodeGen/PowerPC/expand-isel-7.mir
index 4043a45..2540b05 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-7.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-7.mir
@@ -22,9 +22,9 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x3' }
- - { reg: '%x4' }
- - { reg: '%x5' }
+ - { reg: '$x3' }
+ - { reg: '$x4' }
+ - { reg: '$x5' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -41,18 +41,18 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %r4 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r5 = ISEL %r3, %r4, %cr0gt
- ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+ $r4 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r5 = ISEL $r3, $r4, $cr0gt
+ ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK: %[[FALSE:bb.[0-9]+]]
- ; CHECK: %r5 = ORI %r4, 0
+ ; CHECK: $r5 = ORI $r4, 0
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r5 = ADDI %r3, 0
+ ; CHECK: $r5 = ADDI $r3, 0
- %x5 = EXTSW_32_64 %r5
+ $x5 = EXTSW_32_64 $r5
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-8.mir b/llvm/test/CodeGen/PowerPC/expand-isel-8.mir
index c8b857e..719e8be 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-8.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-8.mir
@@ -22,9 +22,9 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x3' }
- - { reg: '%x4' }
- - { reg: '%x5' }
+ - { reg: '$x3' }
+ - { reg: '$x4' }
+ - { reg: '$x5' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -41,25 +41,25 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x3, %x4, %x5
+ liveins: $x3, $x4, $x5
- %r4 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r5 = ISEL %r3, %r4, %cr0gt
- %r3 = ISEL %r4, %r5, %cr0gt
- %r4 = ISEL %r3, %r5, %cr0gt
- ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+ $r4 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r5 = ISEL $r3, $r4, $cr0gt
+ $r3 = ISEL $r4, $r5, $cr0gt
+ $r4 = ISEL $r3, $r5, $cr0gt
+ ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
; CHECK: %[[FALSE:bb.[0-9]+]]
- ; CHECK: %r5 = ORI %r4, 0
- ; CHECK: %r3 = ORI %r5, 0
- ; CHECK: %r4 = ORI %r5, 0
+ ; CHECK: $r5 = ORI $r4, 0
+ ; CHECK: $r3 = ORI $r5, 0
+ ; CHECK: $r4 = ORI $r5, 0
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
; CHECK: [[TRUE]]
- ; CHECK: %r5 = ADDI %r3, 0
- ; CHECK: %r3 = ADDI %r4, 0
- ; CHECK: %r4 = ADDI %r3, 0
+ ; CHECK: $r5 = ADDI $r3, 0
+ ; CHECK: $r3 = ADDI $r4, 0
+ ; CHECK: $r4 = ADDI $r3, 0
- %x5 = EXTSW_32_64 %r5
- %x3 = EXTSW_32_64 %r3
+ $x5 = EXTSW_32_64 $r5
+ $x3 = EXTSW_32_64 $r3
...
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-9.mir b/llvm/test/CodeGen/PowerPC/expand-isel-9.mir
index 5062ddb..0960a8d 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel-9.mir
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-9.mir
@@ -23,8 +23,8 @@
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%x3' }
- - { reg: '%x4' }
+ - { reg: '$x3' }
+ - { reg: '$x4' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -41,14 +41,14 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x3, %x4
+ liveins: $x3, $x4
- %r5 = ADDI %r3, 1
- %cr0 = CMPWI %r3, 0
- %r3 = ISEL %r4, %r4, %cr0gt
+ $r5 = ADDI $r3, 1
+ $cr0 = CMPWI $r3, 0
+ $r3 = ISEL $r4, $r4, $cr0gt
; Test fold ISEL to a copy
- ; CHECK: %r3 = OR %r4, %r4
+ ; CHECK: $r3 = OR $r4, $r4
- %x3 = EXTSW_32_64 %r3
+ $x3 = EXTSW_32_64 $r3
...
diff --git a/llvm/test/CodeGen/PowerPC/fp64-to-int16.ll b/llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
index 360a986..8f11603 100644
--- a/llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ b/llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -10,7 +10,7 @@
; CHECK-NEXT: xori 3, 3, 65534
; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: srwi 3, 3, 5
-; CHECK-NEXT: # implicit-def: %x4
+; CHECK-NEXT: # implicit-def: $x4
; CHECK-NEXT: mr 4, 3
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/livephysregs.mir b/llvm/test/CodeGen/PowerPC/livephysregs.mir
index 6b62687..dbadf57 100644
--- a/llvm/test/CodeGen/PowerPC/livephysregs.mir
+++ b/llvm/test/CodeGen/PowerPC/livephysregs.mir
@@ -4,49 +4,49 @@
# recalculated list if okay and contains all the non-saved and saved CSRs.
# CHECK-LABEL: name: func
# CHECK: bb.3:
-# CHECK-NEXT: liveins: %x30, %x29, %x3, %x6
-# CHECK: %x4 = RLDICR killed %x6, 16, 47
-# CHECK: %x3 = OR8 killed %x4, killed %x3
-# CHECK: BLR8 implicit %lr8, implicit %rm, implicit %x3
+# CHECK-NEXT: liveins: $x30, $x29, $x3, $x6
+# CHECK: $x4 = RLDICR killed $x6, 16, 47
+# CHECK: $x3 = OR8 killed $x4, killed $x3
+# CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
---
name: func
tracksRegLiveness: true
fixedStack:
- - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
- - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' }
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
+ - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$x29' }
- { id: 2, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
body: |
bb.0:
- liveins: %x3, %x5, %x29, %x30
+ liveins: $x3, $x5, $x29, $x30
- %x6 = RLWINM8 %x3, 16, 16, 31
- %x3 = RLDICL killed %x3, 0, 48
- BC undef %cr5lt, %bb.3
+ $x6 = RLWINM8 $x3, 16, 16, 31
+ $x3 = RLDICL killed $x3, 0, 48
+ BC undef $cr5lt, %bb.3
bb.1:
- liveins: %x3, %x6, %x29, %x30
+ liveins: $x3, $x6, $x29, $x30
- %x4 = RLDICR killed %x6, 16, 47
- %x3 = OR8 killed %x4, killed %x3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x4 = RLDICR killed $x6, 16, 47
+ $x3 = OR8 killed $x4, killed $x3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.3:
- liveins: %x3, %x5, %x6, %x29, %x30
+ liveins: $x3, $x5, $x6, $x29, $x30
- dead %x5 = ADD8 %x5, %x6
- BC undef %cr5lt, %bb.1
+ dead $x5 = ADD8 $x5, $x6
+ BC undef $cr5lt, %bb.1
bb.6:
- liveins: %x3, %x6, %x29, %x30
- STD killed %x29, -24, %x1 :: (store 8 into %fixed-stack.1)
- STD killed %x30, -16, %x1 :: (store 8 into %fixed-stack.0, align 16)
- NOP implicit-def dead %x29
- NOP implicit-def dead %x30
+ liveins: $x3, $x6, $x29, $x30
+ STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.1)
+ STD killed $x30, -16, $x1 :: (store 8 into %fixed-stack.0, align 16)
+ NOP implicit-def dead $x29
+ NOP implicit-def dead $x30
- %x30 = LD -16, %x1 :: (load 8 from %fixed-stack.0, align 16)
- %x29 = LD -24, %x1 :: (load 8 from %fixed-stack.1)
+ $x30 = LD -16, $x1 :: (load 8 from %fixed-stack.0, align 16)
+ $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.1)
- %x4 = RLDICR killed %x6, 16, 47
- %x3 = OR8 killed %x4, killed %x3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x4 = RLDICR killed $x6, 16, 47
+ $x3 = OR8 killed $x4, killed $x3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
diff --git a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
index ed6ceec..c43af3b 100644
--- a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
+++ b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
@@ -68,9 +68,9 @@
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %x2
+ liveins: $x2
- %0 = ADDIStocHA %x2, @b
+ %0 = ADDIStocHA $x2, @b
%1 = LD target-flags(ppc-toc-lo) @b, killed %0 :: (load 8 from @b)
%2 = LWZ 0, %1 :: (load 4 from %ir.0)
%3 = LI 0
@@ -83,7 +83,7 @@
STW %4, 0, %1 :: (store 4 into %ir.0)
%10 = EXTSW_32_64 %8
STW %8, 0, %1 :: (store 4 into %ir.0)
- %x3 = COPY %10
- BLR8 implicit %x3, implicit %lr8, implicit %rm
+ $x3 = COPY %10
+ BLR8 implicit $x3, implicit $lr8, implicit $rm
...
diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
index 87197dc..a64cf11 100644
--- a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
+++ b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -7,12 +7,12 @@
%2 = zext i32 %1 to i64
%3 = shl i64 %2, 48
%4 = ashr exact i64 %3, 48
-; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead %cr0
+; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead $cr0
; CHECK: CMPLDI
; CHECK: BCC
-; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def %cr0
-; CHECK: COPY %cr0
+; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def $cr0
+; CHECK: COPY $cr0
; CHECK: BCC
%5 = icmp eq i64 %4, 0
br i1 %5, label %foo, label %bar
@@ -26,8 +26,8 @@
; CHECK-LABEL: fn2
define signext i32 @fn2(i64 %a, i64 %b) {
-; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, implicit-def %cr0
-; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed %cr
+; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, implicit-def $cr0
+; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed $cr
; CHECK: BCC 12, killed [[CREG]]
%1 = or i64 %b, %a
%2 = icmp sgt i64 %1, -1
@@ -42,8 +42,8 @@
; CHECK-LABEL: fn3
define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def %cr0
-; CHECK: [[CREG:[^, ]+]]:crrc = COPY %cr0
+; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def $cr0
+; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0
; CHECK: BCC 76, killed [[CREG]]
%1 = and i32 %a, 10
%2 = icmp ne i32 %1, 0
diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
index bba3e15..1235c10 100644
--- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
+++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
@@ -63,10 +63,10 @@
- { id: 26, class: g8rc_and_g8rc_nox0 }
- { id: 27, class: g8rc_and_g8rc_nox0 }
liveins:
- - { reg: '%x3', virtual-reg: '%6' }
- - { reg: '%x4', virtual-reg: '%7' }
- - { reg: '%x5', virtual-reg: '%8' }
- - { reg: '%x6', virtual-reg: '%9' }
+ - { reg: '$x3', virtual-reg: '%6' }
+ - { reg: '$x4', virtual-reg: '%7' }
+ - { reg: '$x5', virtual-reg: '%8' }
+ - { reg: '$x6', virtual-reg: '%9' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -84,12 +84,12 @@
body: |
bb.0.top:
successors: %bb.1.loop
- liveins: %x3, %x4, %x5, %x6
+ liveins: $x3, $x4, $x5, $x6
- %9 = COPY %x6
- %8 = COPY %x5
- %7 = COPY %x4
- %6 = COPY %x3
+ %9 = COPY $x6
+ %8 = COPY $x5
+ %7 = COPY $x4
+ %6 = COPY $x3
%14 = COPY %9
%13 = COPY %8
%12 = COPY %7
@@ -104,8 +104,8 @@
%1 = PHI %12, %bb.0.top, %5, %bb.3.loop
%2 = PHI %13, %bb.0.top, %4, %bb.3.loop
%3 = PHI %14, %bb.0.top, %5, %bb.3.loop
- %15 = SUBFC8 %3, %1, implicit-def %carry
- %16 = SUBFE8 %2, %0, implicit-def dead %carry, implicit %carry
+ %15 = SUBFC8 %3, %1, implicit-def $carry
+ %16 = SUBFE8 %2, %0, implicit-def dead $carry, implicit $carry
%17 = ADDI8 %16, -1
%18 = ADDI8 %15, -1
%19 = ANDC8 killed %17, %16
@@ -114,8 +114,8 @@
%24 = CNTLZD killed %20
%25 = CMPLDI %15, 0
BCC 76, %25, %bb.2.loop
- ; CHECK: SUBFC8o %3, %1, implicit-def %carry, implicit-def %cr0
- ; CHECK: COPY killed %cr0
+ ; CHECK: SUBFC8o %3, %1, implicit-def $carry, implicit-def $cr0
+ ; CHECK: COPY killed $cr0
; CHECK: BCC
bb.4:
diff --git a/llvm/test/CodeGen/PowerPC/quadint-return.ll b/llvm/test/CodeGen/PowerPC/quadint-return.ll
index b8d982c..ab93e7e 100644
--- a/llvm/test/CodeGen/PowerPC/quadint-return.ll
+++ b/llvm/test/CodeGen/PowerPC/quadint-return.ll
@@ -14,6 +14,6 @@
; CHECK: ********** Function: foo
; CHECK: ********** FAST REGISTER ALLOCATION **********
-; CHECK: %x3 = COPY %{{[0-9]+}}
-; CHECK-NEXT: %x4 = COPY %{{[0-9]+}}
+; CHECK: $x3 = COPY %{{[0-9]+}}
+; CHECK-NEXT: $x4 = COPY %{{[0-9]+}}
; CHECK-NEXT: BLR
diff --git a/llvm/test/CodeGen/PowerPC/scavenging.mir b/llvm/test/CodeGen/PowerPC/scavenging.mir
index a72aaa4..0e772c2 100644
--- a/llvm/test/CodeGen/PowerPC/scavenging.mir
+++ b/llvm/test/CodeGen/PowerPC/scavenging.mir
@@ -5,12 +5,12 @@
tracksRegLiveness: true
body: |
bb.0:
- ; CHECK: [[REG0:%r[0-9]+]] = LI 42
+ ; CHECK: [[REG0:\$r[0-9]+]] = LI 42
; CHECK-NEXT: NOP implicit killed [[REG0]]
%0 : gprc = LI 42
NOP implicit %0
- ; CHECK: [[REG1:%r[0-9]+]] = LI 42
+ ; CHECK: [[REG1:\$r[0-9]+]] = LI 42
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP implicit [[REG1]]
; CHECK-NEXT: NOP
@@ -21,50 +21,50 @@
NOP
NOP implicit %1
- ; CHECK: [[REG2:%r[0-9]+]] = LI 42
+ ; CHECK: [[REG2:\$r[0-9]+]] = LI 42
; CHECK-NEXT: NOP implicit [[REG2]]
%2 : gprc = LI 42
NOP implicit %2
- %x0 = IMPLICIT_DEF
- %x1 = IMPLICIT_DEF
- %x2 = IMPLICIT_DEF
- %x3 = IMPLICIT_DEF
- %x4 = IMPLICIT_DEF
- %x27 = IMPLICIT_DEF
- %x28 = IMPLICIT_DEF
- %x29 = IMPLICIT_DEF
- %x30 = IMPLICIT_DEF
+ $x0 = IMPLICIT_DEF
+ $x1 = IMPLICIT_DEF
+ $x2 = IMPLICIT_DEF
+ $x3 = IMPLICIT_DEF
+ $x4 = IMPLICIT_DEF
+ $x27 = IMPLICIT_DEF
+ $x28 = IMPLICIT_DEF
+ $x29 = IMPLICIT_DEF
+ $x30 = IMPLICIT_DEF
- ; CHECK-NOT: %x0 = LI 42
- ; CHECK-NOT: %x1 = LI 42
- ; CHECK-NOT: %x2 = LI 42
- ; CHECK-NOT: %x3 = LI 42
- ; CHECK-NOT: %x4 = LI 42
- ; CHECK-NOT: %x5 = LI 42
- ; CHECK-NOT: %x27 = LI 42
- ; CHECK-NOT: %x28 = LI 42
- ; CHECK-NOT: %x29 = LI 42
- ; CHECK-NOT: %x30 = LI 42
- ; CHECK: [[REG3:%r[0-9]+]] = LI 42
- ; CHECK-NEXT: %x5 = IMPLICIT_DEF
+ ; CHECK-NOT: $x0 = LI 42
+ ; CHECK-NOT: $x1 = LI 42
+ ; CHECK-NOT: $x2 = LI 42
+ ; CHECK-NOT: $x3 = LI 42
+ ; CHECK-NOT: $x4 = LI 42
+ ; CHECK-NOT: $x5 = LI 42
+ ; CHECK-NOT: $x27 = LI 42
+ ; CHECK-NOT: $x28 = LI 42
+ ; CHECK-NOT: $x29 = LI 42
+ ; CHECK-NOT: $x30 = LI 42
+ ; CHECK: [[REG3:\$r[0-9]+]] = LI 42
+ ; CHECK-NEXT: $x5 = IMPLICIT_DEF
; CHECK-NEXT: NOP implicit killed [[REG2]]
; CHECK-NEXT: NOP implicit killed [[REG3]]
%3 : gprc = LI 42
- %x5 = IMPLICIT_DEF
+ $x5 = IMPLICIT_DEF
NOP implicit %2
NOP implicit %3
- NOP implicit %x0
- NOP implicit %x1
- NOP implicit %x2
- NOP implicit %x3
- NOP implicit %x4
- NOP implicit %x5
- NOP implicit %x27
- NOP implicit %x28
- NOP implicit %x29
- NOP implicit %x30
+ NOP implicit $x0
+ NOP implicit $x1
+ NOP implicit $x2
+ NOP implicit $x3
+ NOP implicit $x4
+ NOP implicit $x5
+ NOP implicit $x27
+ NOP implicit $x28
+ NOP implicit $x29
+ NOP implicit $x30
...
---
# CHECK-LABEL: name: scav0
@@ -76,76 +76,76 @@
- { id: 0, type: variable-sized, offset: -32, alignment: 1 }
body: |
bb.0:
- %x0 = IMPLICIT_DEF
- %x1 = IMPLICIT_DEF
- %x2 = IMPLICIT_DEF
- %x3 = IMPLICIT_DEF
- %x4 = IMPLICIT_DEF
- %x5 = IMPLICIT_DEF
- %x6 = IMPLICIT_DEF
- %x7 = IMPLICIT_DEF
- %x8 = IMPLICIT_DEF
- %x9 = IMPLICIT_DEF
- %x10 = IMPLICIT_DEF
- %x11 = IMPLICIT_DEF
- %x12 = IMPLICIT_DEF
- %x13 = IMPLICIT_DEF
- %x14 = IMPLICIT_DEF
- %x15 = IMPLICIT_DEF
- %x16 = IMPLICIT_DEF
- %x17 = IMPLICIT_DEF
- %x18 = IMPLICIT_DEF
- %x19 = IMPLICIT_DEF
- %x20 = IMPLICIT_DEF
- %x21 = IMPLICIT_DEF
- %x22 = IMPLICIT_DEF
- %x23 = IMPLICIT_DEF
- %x24 = IMPLICIT_DEF
- %x25 = IMPLICIT_DEF
- %x26 = IMPLICIT_DEF
- %x27 = IMPLICIT_DEF
- %x28 = IMPLICIT_DEF
- %x29 = IMPLICIT_DEF
- %x30 = IMPLICIT_DEF
+ $x0 = IMPLICIT_DEF
+ $x1 = IMPLICIT_DEF
+ $x2 = IMPLICIT_DEF
+ $x3 = IMPLICIT_DEF
+ $x4 = IMPLICIT_DEF
+ $x5 = IMPLICIT_DEF
+ $x6 = IMPLICIT_DEF
+ $x7 = IMPLICIT_DEF
+ $x8 = IMPLICIT_DEF
+ $x9 = IMPLICIT_DEF
+ $x10 = IMPLICIT_DEF
+ $x11 = IMPLICIT_DEF
+ $x12 = IMPLICIT_DEF
+ $x13 = IMPLICIT_DEF
+ $x14 = IMPLICIT_DEF
+ $x15 = IMPLICIT_DEF
+ $x16 = IMPLICIT_DEF
+ $x17 = IMPLICIT_DEF
+ $x18 = IMPLICIT_DEF
+ $x19 = IMPLICIT_DEF
+ $x20 = IMPLICIT_DEF
+ $x21 = IMPLICIT_DEF
+ $x22 = IMPLICIT_DEF
+ $x23 = IMPLICIT_DEF
+ $x24 = IMPLICIT_DEF
+ $x25 = IMPLICIT_DEF
+ $x26 = IMPLICIT_DEF
+ $x27 = IMPLICIT_DEF
+ $x28 = IMPLICIT_DEF
+ $x29 = IMPLICIT_DEF
+ $x30 = IMPLICIT_DEF
- ; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]]
+ ; CHECK: STD killed [[SPILLEDREG:\$x[0-9]+]]
; CHECK: [[SPILLEDREG]] = LI8 42
; CHECK: NOP implicit killed [[SPILLEDREG]]
; CHECK: [[SPILLEDREG]] = LD
%0 : g8rc = LI8 42
NOP implicit %0
- NOP implicit %x0
- NOP implicit %x1
- NOP implicit %x2
- NOP implicit %x3
- NOP implicit %x4
- NOP implicit %x5
- NOP implicit %x6
- NOP implicit %x7
- NOP implicit %x8
- NOP implicit %x9
- NOP implicit %x10
- NOP implicit %x11
- NOP implicit %x12
- NOP implicit %x13
- NOP implicit %x14
- NOP implicit %x15
- NOP implicit %x16
- NOP implicit %x17
- NOP implicit %x18
- NOP implicit %x19
- NOP implicit %x20
- NOP implicit %x21
- NOP implicit %x22
- NOP implicit %x23
- NOP implicit %x24
- NOP implicit %x25
- NOP implicit %x26
- NOP implicit %x27
- NOP implicit %x28
- NOP implicit %x29
- NOP implicit %x30
+ NOP implicit $x0
+ NOP implicit $x1
+ NOP implicit $x2
+ NOP implicit $x3
+ NOP implicit $x4
+ NOP implicit $x5
+ NOP implicit $x6
+ NOP implicit $x7
+ NOP implicit $x8
+ NOP implicit $x9
+ NOP implicit $x10
+ NOP implicit $x11
+ NOP implicit $x12
+ NOP implicit $x13
+ NOP implicit $x14
+ NOP implicit $x15
+ NOP implicit $x16
+ NOP implicit $x17
+ NOP implicit $x18
+ NOP implicit $x19
+ NOP implicit $x20
+ NOP implicit $x21
+ NOP implicit $x22
+ NOP implicit $x23
+ NOP implicit $x24
+ NOP implicit $x25
+ NOP implicit $x26
+ NOP implicit $x27
+ NOP implicit $x28
+ NOP implicit $x29
+ NOP implicit $x30
...
---
# Check for bug where we would refuse to spill before the first instruction in a
@@ -153,7 +153,7 @@
# CHECK-LABEL: name: spill_at_begin
# CHECK: bb.0:
# CHECK: liveins:
-# CHECK: STD killed [[REG:%x[0-9]+]]{{.*}}(store 8 into %stack.{{[0-9]+}})
+# CHECK: STD killed [[REG:\$x[0-9]+]]{{.*}}(store 8 into %stack.{{[0-9]+}})
# CHECK: [[REG]] = LIS8 0
# CHECK: [[REG]] = ORI8 killed [[REG]], 48
# CHECK: NOP implicit killed [[REG]]
@@ -166,41 +166,41 @@
- { id: 0, type: variable-sized, offset: -32, alignment: 1 }
body: |
bb.0:
- liveins: %x0, %x1, %x2, %x3, %x4, %x5, %x6, %x7, %x8, %x9, %x10, %x11, %x12, %x13, %x14, %x15, %x16, %x17, %x18, %x19, %x20, %x21, %x22, %x23, %x24, %x25, %x26, %x27, %x28, %x29, %x30, %x31
+ liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
%0 : g8rc = LIS8 0
%1 : g8rc = ORI8 %0, 48
NOP implicit %1
- NOP implicit %x0
- NOP implicit %x1
- NOP implicit %x2
- NOP implicit %x3
- NOP implicit %x4
- NOP implicit %x5
- NOP implicit %x6
- NOP implicit %x7
- NOP implicit %x8
- NOP implicit %x9
- NOP implicit %x10
- NOP implicit %x11
- NOP implicit %x12
- NOP implicit %x13
- NOP implicit %x14
- NOP implicit %x15
- NOP implicit %x16
- NOP implicit %x17
- NOP implicit %x18
- NOP implicit %x19
- NOP implicit %x20
- NOP implicit %x21
- NOP implicit %x22
- NOP implicit %x23
- NOP implicit %x24
- NOP implicit %x25
- NOP implicit %x26
- NOP implicit %x27
- NOP implicit %x28
- NOP implicit %x29
- NOP implicit %x30
- NOP implicit %x31
+ NOP implicit $x0
+ NOP implicit $x1
+ NOP implicit $x2
+ NOP implicit $x3
+ NOP implicit $x4
+ NOP implicit $x5
+ NOP implicit $x6
+ NOP implicit $x7
+ NOP implicit $x8
+ NOP implicit $x9
+ NOP implicit $x10
+ NOP implicit $x11
+ NOP implicit $x12
+ NOP implicit $x13
+ NOP implicit $x14
+ NOP implicit $x15
+ NOP implicit $x16
+ NOP implicit $x17
+ NOP implicit $x18
+ NOP implicit $x19
+ NOP implicit $x20
+ NOP implicit $x21
+ NOP implicit $x22
+ NOP implicit $x23
+ NOP implicit $x24
+ NOP implicit $x25
+ NOP implicit $x26
+ NOP implicit $x27
+ NOP implicit $x28
+ NOP implicit $x29
+ NOP implicit $x30
+ NOP implicit $x31
...
diff --git a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
index d45a83d..49c645f 100644
--- a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
+++ b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
@@ -27,7 +27,7 @@
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x2' }
+ - { reg: '$x2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -50,17 +50,17 @@
constants:
body: |
bb.0.entry:
- liveins: %x2
- %0 = ADDIStlsgdHA %x2, @tls_var
- %1 = ADDItlsgdLADDR killed %0, @tls_var, @tls_var, implicit-def dead %x0, implicit-def dead %x3, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def dead %lr8, implicit-def dead %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
+ liveins: $x2
+ %0 = ADDIStlsgdHA $x2, @tls_var
+ %1 = ADDItlsgdLADDR killed %0, @tls_var, @tls_var, implicit-def dead $x0, implicit-def dead $x3, implicit-def dead $x4, implicit-def dead $x5, implicit-def dead $x6, implicit-def dead $x7, implicit-def dead $x8, implicit-def dead $x9, implicit-def dead $x10, implicit-def dead $x11, implicit-def dead $x12, implicit-def dead $lr8, implicit-def dead $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead $cr6, implicit-def dead $cr7
%2 = LWZ8 0, killed %1 :: (dereferenceable load 4 from @tls_var)
- %x3 = COPY %2
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
; CHECK-LABEL: bb.0.entry
- ; CHECK: %[[reg1:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStlsgdHA %x2, @tls_var
+ ; CHECK: %[[reg1:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStlsgdHA $x2, @tls_var
; CHECK: ADJCALLSTACKDOWN 0, 0
- ; CHECK: %x3 = ADDItlsgdL %[[reg1]], @tls_var
- ; CHECK: %x3 = GETtlsADDR %x3, @tls_var
+ ; CHECK: $x3 = ADDItlsgdL %[[reg1]], @tls_var
+ ; CHECK: $x3 = GETtlsADDR $x3, @tls_var
; CHECK: ADJCALLSTACKUP 0, 0
; CHECK: BLR8
...
diff --git a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir
index 2bb8814..660fb2c 100644
--- a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir
+++ b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir
@@ -27,7 +27,7 @@
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
liveins:
- - { reg: '%x2' }
+ - { reg: '$x2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -50,14 +50,14 @@
constants:
body: |
bb.0.entry:
- liveins: %x2
- ADJCALLSTACKDOWN 32, 0, implicit-def %r1, implicit %r1
- %0 = ADDIStlsgdHA %x2, @tls_var
- %1 = ADDItlsgdLADDR killed %0, @tls_var, @tls_var, implicit-def dead %x0, implicit-def dead %x3, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def dead %lr8, implicit-def dead %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
+ liveins: $x2
+ ADJCALLSTACKDOWN 32, 0, implicit-def $r1, implicit $r1
+ %0 = ADDIStlsgdHA $x2, @tls_var
+ %1 = ADDItlsgdLADDR killed %0, @tls_var, @tls_var, implicit-def dead $x0, implicit-def dead $x3, implicit-def dead $x4, implicit-def dead $x5, implicit-def dead $x6, implicit-def dead $x7, implicit-def dead $x8, implicit-def dead $x9, implicit-def dead $x10, implicit-def dead $x11, implicit-def dead $x12, implicit-def dead $lr8, implicit-def dead $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead $cr6, implicit-def dead $cr7
%2 = LWZ8 0, killed %1 :: (dereferenceable load 4 from @tls_var)
- %x3 = COPY %2
- ADJCALLSTACKUP 32, 0, implicit-def %r1, implicit %r1
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %2
+ ADJCALLSTACKUP 32, 0, implicit-def $r1, implicit $r1
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
; CHECK-LABEL: bb.0.entry
; CHECK-NOT: ADJCALLSTACKDOWN 0, 0
; CHECK-NOT: ADJCALLSTACKUP 0, 0