Drop support for Mips1 and Mips2.
llvm-svn: 139405
diff --git a/llvm/test/CodeGen/Mips/2010-07-20-Select.ll b/llvm/test/CodeGen/Mips/2010-07-20-Select.ll
index 31e56ff..cc2e3ca 100644
--- a/llvm/test/CodeGen/Mips/2010-07-20-Select.ll
+++ b/llvm/test/CodeGen/Mips/2010-07-20-Select.ll
@@ -1,7 +1,10 @@
-; RUN: llc < %s -march=mips -relocation-model=static -mcpu=mips1 | FileCheck %s
-; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic -mcpu=mips1 | FileCheck %s
+; DISABLED: llc < %s -march=mips -relocation-model=static | FileCheck %s
+; DISABLED: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
+; RUN: false
++; XFAIL: *
; Fix PR7473
+
define i32 @main() nounwind readnone {
entry:
%a = alloca i32, align 4 ; <i32*> [#uses=2]
diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll
index 50bcc091..bc6bf5f 100644
--- a/llvm/test/CodeGen/Mips/atomic.ll
+++ b/llvm/test/CodeGen/Mips/atomic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | FileCheck %s
declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
diff --git a/llvm/test/CodeGen/Mips/fpcmp.ll b/llvm/test/CodeGen/Mips/fpcmp.ll
index 24de2ff..13ac283 100644
--- a/llvm/test/CodeGen/Mips/fpcmp.ll
+++ b/llvm/test/CodeGen/Mips/fpcmp.ll
@@ -1,5 +1,4 @@
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
-; RUN: llc < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
@g1 = external global i32
@@ -9,10 +8,6 @@
; CHECK-MIPS32R2: movt
; CHECK-MIPS32R2: c.olt.s
; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1t
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1t
%cmp = fcmp olt float %f0, %f1
%conv = zext i1 %cmp to i32
%tmp2 = load i32* @g1, align 4
diff --git a/llvm/test/CodeGen/Mips/frame-address.ll b/llvm/test/CodeGen/Mips/frame-address.ll
index c48ce7e..9df1808 100644
--- a/llvm/test/CodeGen/Mips/frame-address.ll
+++ b/llvm/test/CodeGen/Mips/frame-address.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | FileCheck %s
declare i8* @llvm.frameaddress(i32) nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/mips1f64ldst.ll b/llvm/test/CodeGen/Mips/mips1f64ldst.ll
deleted file mode 100644
index 28683be..0000000
--- a/llvm/test/CodeGen/Mips/mips1f64ldst.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc < %s -march=mips -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EB
-
-@g1 = common global double 0.000000e+00, align 8
-@g2 = common global double 0.000000e+00, align 8
-
-define double @foo0(double %d0) nounwind {
-entry:
-; CHECK-EL: lw $[[R0:[0-9]+]], %got($CPI0_0)
-; CHECK-EL: lwc1 $f[[R1:[0-9]+]], %lo($CPI0_0)($[[R0]])
-; CHECK-EL: lwc1 $f{{[0-9]+}}, %lo($CPI0_0+4)($[[R0]])
-; CHECK-EL: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
-; CHECK-EL: lw $[[R3:[0-9]+]], %got(g1)
-; CHECK-EL: swc1 $f[[R2]], 0($[[R3]])
-; CHECK-EL: swc1 $f{{[0-9]+}}, 4($[[R3]])
-; CHECK-EL: lw $[[R4:[0-9]+]], %got(g2)
-; CHECK-EL: lwc1 $f0, 0($[[R4]])
-; CHECK-EL: lwc1 $f1, 4($[[R4]])
-
-; CHECK-EB: lw $[[R0:[0-9]+]], %got($CPI0_0)
-; CHECK-EB: lwc1 $f{{[0-9]+}}, %lo($CPI0_0)($[[R0]])
-; CHECK-EB: lwc1 $f[[R1:[0-9]+]], %lo($CPI0_0+4)($[[R0]])
-; CHECK-EB: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
-; CHECK-EB: lw $[[R3:[0-9]+]], %got(g1)
-; CHECK-EB: swc1 $f{{[0-9]+}}, 0($[[R3]])
-; CHECK-EB: swc1 $f[[R2]], 4($[[R3]])
-; CHECK-EB: lw $[[R4:[0-9]+]], %got(g2)
-; CHECK-EB: lwc1 $f1, 0($[[R4]])
-; CHECK-EB: lwc1 $f0, 4($[[R4]])
-
- %add = fadd double %d0, 2.000000e+00
- store double %add, double* @g1, align 8
- %tmp1 = load double* @g2, align 8
- ret double %tmp1
-}
-
diff --git a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
index 14ce04b..4a3d9ab 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s
+; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s
; All test functions do the same thing - they return the first variable
diff --git a/llvm/test/CodeGen/Mips/select.ll b/llvm/test/CodeGen/Mips/select.ll
index 623c2a3..e79d65f 100644
--- a/llvm/test/CodeGen/Mips/select.ll
+++ b/llvm/test/CodeGen/Mips/select.ll
@@ -1,5 +1,4 @@
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
-; RUN: llc < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
@d2 = external global double
@d3 = external global double
@@ -7,7 +6,6 @@
define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
entry:
; CHECK-MIPS32R2: movn
-; CHECK-MIPS1: beq
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, i32 %f1, i32 %f0
ret i32 %cond
@@ -16,7 +14,6 @@
define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
entry:
; CHECK-MIPS32R2: movn.s
-; CHECK-MIPS1: beq
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, float %f0, float %f1
ret float %cond
@@ -25,7 +22,6 @@
define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
entry:
; CHECK-MIPS32R2: movn.d
-; CHECK-MIPS1: bne
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, double %f0, double %f1
ret double %cond
@@ -35,8 +31,6 @@
entry:
; CHECK-MIPS32R2: c.eq.s
; CHECK-MIPS32R2: movt.s
-; CHECK-MIPS1: c.eq.s
-; CHECK-MIPS1: bc1f
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@@ -46,8 +40,6 @@
entry:
; CHECK-MIPS32R2: c.olt.s
; CHECK-MIPS32R2: movt.s
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1f
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@@ -57,8 +49,6 @@
entry:
; CHECK-MIPS32R2: c.ule.s
; CHECK-MIPS32R2: movf.s
-; CHECK-MIPS1: c.ule.s
-; CHECK-MIPS1: bc1t
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@@ -68,8 +58,6 @@
entry:
; CHECK-MIPS32R2: c.ule.s
; CHECK-MIPS32R2: movf.d
-; CHECK-MIPS1: c.ule.s
-; CHECK-MIPS1: bc1t
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@@ -79,8 +67,6 @@
entry:
; CHECK-MIPS32R2: c.eq.d
; CHECK-MIPS32R2: movt.d
-; CHECK-MIPS1: c.eq.d
-; CHECK-MIPS1: bc1f
%cmp = fcmp oeq double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@@ -90,8 +76,6 @@
entry:
; CHECK-MIPS32R2: c.olt.d
; CHECK-MIPS32R2: movt.d
-; CHECK-MIPS1: c.olt.d
-; CHECK-MIPS1: bc1f
%cmp = fcmp olt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@@ -101,8 +85,6 @@
entry:
; CHECK-MIPS32R2: c.ule.d
; CHECK-MIPS32R2: movf.d
-; CHECK-MIPS1: c.ule.d
-; CHECK-MIPS1: bc1t
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@@ -112,8 +94,6 @@
entry:
; CHECK-MIPS32R2: c.ule.d
; CHECK-MIPS32R2: movf.s
-; CHECK-MIPS1: c.ule.d
-; CHECK-MIPS1: bc1t
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@@ -123,8 +103,6 @@
entry:
; CHECK-MIPS32R2: c.eq.s
; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.eq.s
-; CHECK-MIPS1: bc1f
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
@@ -134,8 +112,6 @@
entry:
; CHECK-MIPS32R2: c.olt.s
; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1f
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
@@ -145,8 +121,6 @@
entry:
; CHECK-MIPS32R2: c.ule.s
; CHECK-MIPS32R2: movf
-; CHECK-MIPS1: c.ule.s
-; CHECK-MIPS1: bc1t
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
@@ -156,8 +130,6 @@
entry:
; CHECK-MIPS32R2: c.eq.d
; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.eq.d
-; CHECK-MIPS1: bc1f
%tmp = load double* @d2, align 8, !tbaa !0
%tmp1 = load double* @d3, align 8, !tbaa !0
%cmp = fcmp oeq double %tmp, %tmp1
@@ -169,8 +141,6 @@
entry:
; CHECK-MIPS32R2: c.olt.d
; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.olt.d
-; CHECK-MIPS1: bc1f
%tmp = load double* @d2, align 8, !tbaa !0
%tmp1 = load double* @d3, align 8, !tbaa !0
%cmp = fcmp olt double %tmp, %tmp1
@@ -182,8 +152,6 @@
entry:
; CHECK-MIPS32R2: c.ule.d
; CHECK-MIPS32R2: movf
-; CHECK-MIPS1: c.ule.d
-; CHECK-MIPS1: bc1t
%tmp = load double* @d2, align 8, !tbaa !0
%tmp1 = load double* @d3, align 8, !tbaa !0
%cmp = fcmp ogt double %tmp, %tmp1
diff --git a/llvm/test/CodeGen/Mips/tls.ll b/llvm/test/CodeGen/Mips/tls.ll
index 034738b..b0474b4 100644
--- a/llvm/test/CodeGen/Mips/tls.ll
+++ b/llvm/test/CodeGen/Mips/tls.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC
-; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=PIC
+; RUN: llc -march=mipsel -relocation-model=static < %s \
; RUN: | FileCheck %s -check-prefix=STATIC