Stop producing .data.rel sections.
If a section is rw, it is irrelevant if the dynamic linker will write to
it or not.
It looks like llvm implemented this because gcc was doing it. It looks
like gcc implemented this in the hope that it would put all the
relocated items close together and speed up the dynamic linker.
There are two problem with this:
* It doesn't work. Both bfd and gold will map .data.rel to .data and
concatenate the input sections in the order they are seen.
* If we want a feature like that, it can be implemented directly in the
linker since it knowns where the dynamic relocations are.
llvm-svn: 253436
diff --git a/llvm/test/CodeGen/AArch64/emutls_generic.ll b/llvm/test/CodeGen/AArch64/emutls_generic.ll
index b06c647..7664db3 100644
--- a/llvm/test/CodeGen/AArch64/emutls_generic.ll
+++ b/llvm/test/CodeGen/AArch64/emutls_generic.ll
@@ -47,7 +47,7 @@
; ARM_64: .section .rodata,
; ARM_64-LABEL: __emutls_t.external_y:
; ARM_64-NEXT: .byte 7
-; ARM_64: .section .data.rel
+; ARM_64: .data
; ARM_64: .align 3
; ARM_64-LABEL: __emutls_v.internal_y:
; ARM_64-NEXT: .xword 8
diff --git a/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll b/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll
index 143558f..c59a5b6 100644
--- a/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll
+++ b/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll
@@ -15,7 +15,7 @@
; CHECK-NEXT: .xword .L_ZTIi.DW.stub-[[TYPEINFO_LBL]]
; .. and which is properly defined (in a writable section for the dynamic loader) later.
-; CHECK: .section .data.rel,"aw"
+; CHECK: .data
; CHECK: .L_ZTIi.DW.stub:
; CHECK-NEXT: .xword _ZTIi
diff --git a/llvm/test/CodeGen/ARM/emutls_generic.ll b/llvm/test/CodeGen/ARM/emutls_generic.ll
index b6f745d..0fada88 100644
--- a/llvm/test/CodeGen/ARM/emutls_generic.ll
+++ b/llvm/test/CodeGen/ARM/emutls_generic.ll
@@ -39,7 +39,7 @@
; ARM_32: .long __emutls_v.internal_y
; ARM_32-NOT: __emutls_t.external_x
; ARM_32-NOT: __emutls_v.external_x:
-; ARM_32: .section .data.rel
+; ARM_32: .data
; ARM_32: .align 2
; ARM_32-LABEL: __emutls_v.external_y:
; ARM_32-NEXT: .long 1
@@ -49,7 +49,7 @@
; ARM_32: .section .rodata,
; ARM_32-LABEL: __emutls_t.external_y:
; ARM_32-NEXT: .byte 7
-; ARM_32: .section .data.rel
+; ARM_32: .data
; ARM_32: .align 2
; ARM_32-LABEL: __emutls_v.internal_y:
; ARM_32-NEXT: .long 8
diff --git a/llvm/test/CodeGen/Mips/emutls_generic.ll b/llvm/test/CodeGen/Mips/emutls_generic.ll
index 6d0bb33..a6cf23a 100644
--- a/llvm/test/CodeGen/Mips/emutls_generic.ll
+++ b/llvm/test/CodeGen/Mips/emutls_generic.ll
@@ -30,13 +30,13 @@
; MIPS_32: lw {{.+}}call16(__emutls_get_address
; MIPS_32-NOT: __emutls_t.external_x
; MIPS_32-NOT: __emutls_v.external_x:
-; MIPS_32: .section .data.rel
+; MIPS_32: .data
; MIPS_32: .align 2
; MIPS_32-LABEL: __emutls_v.external_y:
; MIPS_32: .section .rodata,
; MIPS_32-LABEL: __emutls_t.external_y:
; MIPS_32-NEXT: .byte 7
-; MIPS_32: .section .data.rel
+; MIPS_32: .data
; MIPS_32: .align 2
; MIPS_32-LABEL: __emutls_v.internal_y:
; MIPS_32-NEXT: .4byte 8
@@ -58,7 +58,7 @@
; MIPS_64: .section .rodata,
; MIPS_64-LABEL: __emutls_t.external_y:
; MIPS_64-NEXT: .byte 7
-; MIPS_64: .section .data.rel
+; MIPS_64: .data
; MIPS_64: .align 3
; MIPS_64-LABEL: __emutls_v.internal_y:
; MIPS_64-NEXT: .8byte 8
diff --git a/llvm/test/CodeGen/X86/emutls-pic.ll b/llvm/test/CodeGen/X86/emutls-pic.ll
index 1c4d837..11676af 100644
--- a/llvm/test/CodeGen/X86/emutls-pic.ll
+++ b/llvm/test/CodeGen/X86/emutls-pic.ll
@@ -103,7 +103,7 @@
;;;;; 32-bit targets
-; X32: .section .data.rel,
+; X32: .data
; X32-LABEL: __emutls_v.i:
; X32-NEXT: .long 4
; X32-NEXT: .long 4
@@ -114,7 +114,7 @@
; X32-LABEL: __emutls_t.i:
; X32-NEXT: .long 15
-; X32: .section .data.rel,
+; X32: .data
; X32-LABEL: __emutls_v.j:
; X32-NEXT: .long 4
; X32-NEXT: .long 4
@@ -136,7 +136,7 @@
;;;;; 64-bit targets
-; X64: .section .data.rel,
+; X64: .data
; X64-LABEL: __emutls_v.i:
; X64-NEXT: .quad 4
; X64-NEXT: .quad 4
@@ -147,7 +147,7 @@
; X64-LABEL: __emutls_t.i:
; X64-NEXT: .long 15
-; X64: .section .data.rel,
+; X64: .data
; X64-LABEL: __emutls_v.j:
; X64-NEXT: .quad 4
; X64-NEXT: .quad 4
diff --git a/llvm/test/CodeGen/X86/emutls-pie.ll b/llvm/test/CodeGen/X86/emutls-pie.ll
index 92a7b16..4970b14 100644
--- a/llvm/test/CodeGen/X86/emutls-pie.ll
+++ b/llvm/test/CodeGen/X86/emutls-pie.ll
@@ -100,7 +100,7 @@
;;;;; 32-bit targets
-; X32: .section .data.rel,
+; X32: .data
; X32-LABEL: __emutls_v.i:
; X32-NEXT: .long 4
; X32-NEXT: .long 4
@@ -116,7 +116,7 @@
;;;;; 64-bit targets
-; X64: .section .data.rel,
+; X64: .data
; X64-LABEL: __emutls_v.i:
; X64-NEXT: .quad 4
; X64-NEXT: .quad 4
diff --git a/llvm/test/CodeGen/X86/emutls_generic.ll b/llvm/test/CodeGen/X86/emutls_generic.ll
index 480543d..b99a195 100644
--- a/llvm/test/CodeGen/X86/emutls_generic.ll
+++ b/llvm/test/CodeGen/X86/emutls_generic.ll
@@ -55,7 +55,7 @@
; X86_32: calll __emutls_get_address
; X86_32-NOT: __emutls_t.external_x
; X86_32-NOT: __emutls_v.external_x:
-; X86_32: .section .data.rel
+; X86_32: .data
; X86_32: .align 4
; X86_32-LABEL: __emutls_v.external_y:
; X86_32-NEXT: .long 1
@@ -65,7 +65,7 @@
; X86_32: .section .rodata,
; X86_32-LABEL: __emutls_t.external_y:
; X86_32-NEXT: .byte 7
-; X86_32: .section .data.rel
+; X86_32: .data
; X86_32: .align 4
; X86_32-LABEL: __emutls_v.internal_y:
; X86_32-NEXT: .long 8
@@ -95,7 +95,7 @@
; X86_64: .section .rodata,
; X86_64-LABEL: __emutls_t.external_y:
; X86_64-NEXT: .byte 7
-; X86_64: .section .data.rel
+; X86_64: .data
; X86_64: .align 8
; X86_64-LABEL: __emutls_v.internal_y:
; X86_64-NEXT: .quad 8
diff --git a/llvm/test/CodeGen/X86/rodata-relocs.ll b/llvm/test/CodeGen/X86/rodata-relocs.ll
index 7bd129b..6379ef1 100644
--- a/llvm/test/CodeGen/X86/rodata-relocs.ll
+++ b/llvm/test/CodeGen/X86/rodata-relocs.ll
@@ -38,7 +38,7 @@
; PIC-NOT: .section
; PIC: p1:
; PIC: t1:
-; PIC: .section .data.rel,"aw",@progbits
+; PIC: .data
; PIC: p2:
; PIC: t2:
; PIC-NOT: .section