commit 44f6d694b38a6294503da3464c778b021c2da42d
author Matt Arsenault <Matthew.Arsenault@amd.com> Sat Aug 13 01:43:46 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Sat Aug 13 01:43:46 2016 +0000
tree ec24d911e49a7d7c516efede6f297ab6460780f7
parent 0dd9ed1d452e528cc0a8616cc185d9043afb76db

AMDGPU/R600: Remove macros

llvm-svn: 278588

llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 560fe0a..ad3f481 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -328,7 +328,7 @@
         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
                 AMDGPU::PREDICATE_BIT)
             .addOperand(MI.getOperand(1))
-            .addImm(OPCODE_IS_NOT_ZERO)
+            .addImm(AMDGPU::PRED_SETNE)
             .addImm(0); // Flags
     TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
@@ -342,7 +342,7 @@
         BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
                 AMDGPU::PREDICATE_BIT)
             .addOperand(MI.getOperand(1))
-            .addImm(OPCODE_IS_NOT_ZERO_INT)
+            .addImm(AMDGPU::PRED_SETNE_INT)
             .addImm(0); // Flags
     TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))