AMDGPU/R600: Remove macros
llvm-svn: 278588
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 573b187..e29fc46 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -910,17 +910,17 @@
R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
MachineOperand &MO = Cond[1];
switch (MO.getImm()) {
- case OPCODE_IS_ZERO_INT:
- MO.setImm(OPCODE_IS_NOT_ZERO_INT);
+ case AMDGPU::PRED_SETE_INT:
+ MO.setImm(AMDGPU::PRED_SETNE_INT);
break;
- case OPCODE_IS_NOT_ZERO_INT:
- MO.setImm(OPCODE_IS_ZERO_INT);
+ case AMDGPU::PRED_SETNE_INT:
+ MO.setImm(AMDGPU::PRED_SETE_INT);
break;
- case OPCODE_IS_ZERO:
- MO.setImm(OPCODE_IS_NOT_ZERO);
+ case AMDGPU::PRED_SETE:
+ MO.setImm(AMDGPU::PRED_SETNE);
break;
- case OPCODE_IS_NOT_ZERO:
- MO.setImm(OPCODE_IS_ZERO);
+ case AMDGPU::PRED_SETNE:
+ MO.setImm(AMDGPU::PRED_SETE);
break;
default:
return true;
@@ -1478,11 +1478,3 @@
FlagOp.setImm(InstFlags);
}
}
-
-bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const {
- return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
-}
-
-bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const {
- return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
-}