[SystemZ] Add MC support for interlocked-access 1 instructions
llvm-svn: 197984
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index a8efe16..50badf8 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -531,6 +531,10 @@
// Ternary:
// One register output operand and three register input operands.
//
+// LoadAndOp:
+// One output operand and two input operands. The first input operand
+// is a register and the second is an address.
+//
// CmpSwap:
// One output operand and three input operands. The first two
// operands are registers and the third is an address. The instruction
@@ -1267,6 +1271,15 @@
let AccessBytes = bytes;
}
+class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+ RegisterOperand cls, AddressingMode mode = bdaddr20only>
+ : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
+ mnemonic#"\t$R1, $R3, $BD2",
+ [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
+ let mayLoad = 1;
+ let mayStore = 1;
+}
+
class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls, AddressingMode mode = bdaddr12only>
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 587b170..91c3d3c 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1203,6 +1203,19 @@
def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
+let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
+ def LAA : LoadAndOpRSY<"laa", 0xEBF8, null_frag, GR32>;
+ def LAAG : LoadAndOpRSY<"laag", 0xEBE8, null_frag, GR64>;
+ def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>;
+ def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
+ def LAN : LoadAndOpRSY<"lan", 0xEBF4, null_frag, GR32>;
+ def LANG : LoadAndOpRSY<"lang", 0xEBE4, null_frag, GR64>;
+ def LAO : LoadAndOpRSY<"lao", 0xEBF6, null_frag, GR32>;
+ def LAOG : LoadAndOpRSY<"laog", 0xEBE6, null_frag, GR64>;
+ def LAX : LoadAndOpRSY<"lax", 0xEBF7, null_frag, GR32>;
+ def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, null_frag, GR64>;
+}
+
def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
diff --git a/llvm/lib/Target/SystemZ/SystemZProcessors.td b/llvm/lib/Target/SystemZ/SystemZProcessors.td
index 9aed4f9..b3df317 100644
--- a/llvm/lib/Target/SystemZ/SystemZProcessors.td
+++ b/llvm/lib/Target/SystemZ/SystemZProcessors.td
@@ -41,11 +41,18 @@
"Assume that the fast-serialization facility is installed"
>;
+def FeatureInterlockedAccess1 : SystemZFeature<
+ "interlocked-access1", "InterlockedAccess1",
+ "Assume that interlocked-access facility 1 is installed"
+>;
+
def : Processor<"generic", NoItineraries, []>;
def : Processor<"z10", NoItineraries, []>;
def : Processor<"z196", NoItineraries,
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
- FeatureFPExtension, FeatureFastSerialization]>;
+ FeatureFPExtension, FeatureFastSerialization,
+ FeatureInterlockedAccess1]>;
def : Processor<"zEC12", NoItineraries,
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
- FeatureFPExtension, FeatureFastSerialization]>;
+ FeatureFPExtension, FeatureFastSerialization,
+ FeatureInterlockedAccess1]>;
diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
index 333db25..5a85a043 100644
--- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -26,7 +26,8 @@
const std::string &FS)
: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
- HasFastSerialization(false), TargetTriple(TT) {
+ HasFastSerialization(false), HasInterlockedAccess1(false),
+ TargetTriple(TT) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "generic";
diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h
index 6823c14..f7c8f96 100644
--- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h
+++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h
@@ -33,6 +33,7 @@
bool HasHighWord;
bool HasFPExtension;
bool HasFastSerialization;
+ bool HasInterlockedAccess1;
private:
Triple TargetTriple;
@@ -62,6 +63,9 @@
// Return true if the target has the fast-serialization facility.
bool hasFastSerialization() const { return HasFastSerialization; }
+ // Return true if the target has interlocked-access facility 1.
+ bool hasInterlockedAccess1() const { return HasInterlockedAccess1; }
+
// Return true if GV can be accessed using LARL for reloc model RM
// and code model CM.
bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,