R600 -> AMDGPU rename
llvm-svn: 239657
diff --git a/llvm/docs/R600Usage.rst b/llvm/docs/AMDGPUUsage.rst
similarity index 91%
rename from llvm/docs/R600Usage.rst
rename to llvm/docs/AMDGPUUsage.rst
index 9bd16f4..3cb41ce 100644
--- a/llvm/docs/R600Usage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1,11 +1,11 @@
-============================
-User Guide for R600 Back-end
-============================
+==============================
+User Guide for AMDGPU Back-end
+==============================
Introduction
============
-The R600 back-end provides ISA code generation for AMD GPUs, starting with
+The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with
the R600 family up until the current Volcanic Islands (GCN Gen 3).
@@ -14,7 +14,7 @@
The assembler is currently considered experimental.
-For syntax examples look in test/MC/R600.
+For syntax examples look in test/MC/AMDGPU.
Below some of the currently supported features (modulo bugs). These
all apply to the Southern Islands ISA, Sea Islands and Volcanic Islands
diff --git a/llvm/docs/CompilerWriterInfo.rst b/llvm/docs/CompilerWriterInfo.rst
index 2dfdc9b..900ba24 100644
--- a/llvm/docs/CompilerWriterInfo.rst
+++ b/llvm/docs/CompilerWriterInfo.rst
@@ -68,8 +68,8 @@
* `PowerPC64 alignment of long doubles (from GCC) <http://gcc.gnu.org/ml/gcc-patches/2003-09/msg00997.html>`_
* `Long branch stubs for powerpc64-linux (from binutils) <http://sources.redhat.com/ml/binutils/2002-04/msg00573.html>`_
-R600
-----
+AMDGPU
+------
* `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf>`_
* `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf>`_
diff --git a/llvm/docs/GettingStarted.rst b/llvm/docs/GettingStarted.rst
index 18b3c1d..212fa0b 100644
--- a/llvm/docs/GettingStarted.rst
+++ b/llvm/docs/GettingStarted.rst
@@ -711,7 +711,7 @@
| | as ``LLVM_ALL_TARGETS``, and can be set to include |
| | out-of-tree targets. The default value includes: |
| | ``AArch64, ARM, CppBackend, Hexagon, |
-| | Mips, MSP430, NVPTX, PowerPC, R600, Sparc, |
+| | Mips, MSP430, NVPTX, PowerPC, AMDGPU, Sparc, |
| | SystemZ, X86, XCore``. |
+-------------------------+----------------------------------------------------+
| LLVM_ENABLE_DOXYGEN | Build doxygen-based documentation from the source |
diff --git a/llvm/docs/index.rst b/llvm/docs/index.rst
index 2cc5b8b..0b68118 100644
--- a/llvm/docs/index.rst
+++ b/llvm/docs/index.rst
@@ -252,7 +252,7 @@
WritingAnLLVMPass
HowToUseAttributes
NVPTXUsage
- R600Usage
+ AMDGPUUsage
StackMaps
InAlloca
BigEndianNEON
@@ -338,8 +338,8 @@
:doc:`NVPTXUsage`
This document describes using the NVPTX back-end to compile GPU kernels.
-:doc:`R600Usage`
- This document describes how to use the R600 back-end.
+:doc:`AMDGPUUsage`
+ This document describes how to use the AMDGPU back-end.
:doc:`StackMaps`
LLVM support for mapping instruction addresses to the location of