[AMDGPU][MC][GFX10] Enabled null for 64-bit dst operands
See https://bugs.llvm.org/show_bug.cgi?id=43524
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D68785
llvm-svn: 374557
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 9ef8b30..75e0fb8 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -290,6 +290,10 @@
return isOff() || isVReg32();
}
+ bool isNull() const {
+ return isRegKind() && getReg() == AMDGPU::SGPR_NULL;
+ }
+
bool isSDWAOperand(MVT type) const;
bool isSDWAFP16Operand() const;
bool isSDWAFP32Operand() const;
@@ -6976,6 +6980,14 @@
return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;
case MCK_AttrChan:
return Operand.isAttrChan() ? Match_Success : Match_InvalidOperand;
+ case MCK_SReg_64:
+ case MCK_SReg_64_XEXEC:
+ // Null is defined as a 32-bit register but
+ // it should also be enabled with 64-bit operands.
+ // The following code enables it for SReg_64 operands
+ // used as source and destination. Remaining source
+ // operands are handled in isInlinableImm.
+ return Operand.isNull() ? Match_Success : Match_InvalidOperand;
default:
return Match_InvalidOperand;
}