[llvm-mca] Move the logic that updates the register files from InstrBuilder to DispatchUnit. NFCI
Before this patch, the register file was always updated at instruction creation
time. That means, new read-after-write dependencies, and new temporary registers
were allocated at instruction creation time.
This patch refactors the code in InstrBuilder, and move all the logic that
updates the register file into the dispatch unit. We only want to update the
register file when instructions are effectively dispatched (not before).
This refactoring also helps removing a bad dependency between the InstrBuilder
and the DispatchUnit.
No functional change intended.
llvm-svn: 327514
diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp
index 35b3a35..7c9ffdc 100644
--- a/llvm/tools/llvm-mca/InstrBuilder.cpp
+++ b/llvm/tools/llvm-mca/InstrBuilder.cpp
@@ -419,14 +419,12 @@
}
Instruction *InstrBuilder::createInstruction(const MCSubtargetInfo &STI,
- DispatchUnit &DU, unsigned Idx,
- const MCInst &MCI) {
+ unsigned Idx, const MCInst &MCI) {
const InstrDesc &D = getOrCreateInstrDesc(STI, MCI);
Instruction *NewIS = new Instruction(D);
// Populate Reads first.
const MCSchedModel &SM = STI.getSchedModel();
- SmallVector<WriteState *, 4> DependentWrites;
for (const ReadDescriptor &RD : D.Reads) {
int RegID = -1;
if (RD.OpIndex != -1) {
@@ -447,34 +445,9 @@
// Okay, this is a register operand. Create a ReadState for it.
assert(RegID > 0 && "Invalid register ID found!");
- ReadState *NewRDS = new ReadState(RD);
+ ReadState *NewRDS = new ReadState(RD, RegID);
NewIS->getUses().emplace_back(std::unique_ptr<ReadState>(NewRDS));
- DU.collectWrites(DependentWrites, RegID);
- NewRDS->setDependentWrites(DependentWrites.size());
- DEBUG(dbgs() << "Found " << DependentWrites.size()
- << " dependent writes\n");
-
- // We know that this read depends on all the writes in DependentWrites.
- // For each write, check if we have ReadAdvance information, and use it
- // to figure out after how many cycles this read becomes available.
- if (!RD.HasReadAdvanceEntries) {
- for (WriteState *WS : DependentWrites)
- WS->addUser(NewRDS, /* ReadAdvance */ 0);
- // Prepare the set for another round.
- DependentWrites.clear();
- continue;
- }
-
- const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
- for (WriteState *WS : DependentWrites) {
- unsigned WriteResID = WS->getWriteResourceID();
- int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.OpIndex, WriteResID);
- WS->addUser(NewRDS, ReadAdvance);
- }
-
- // Prepare the set for another round.
- DependentWrites.clear();
- }
+ }
// Now populate writes.
for (const WriteDescriptor &WD : D.Writes) {
@@ -489,11 +462,8 @@
WriteState *NewWS = new WriteState(WD);
NewIS->getDefs().emplace_back(std::unique_ptr<WriteState>(NewWS));
NewWS->setRegisterID(RegID);
- DU.addNewRegisterMapping(*NewWS);
}
- // Update Latency.
- NewIS->setCyclesLeft(D.MaxLatency);
return NewIS;
}