commit 474aac4da92875cb2826b6654b90821b10ebf65b
author Chris Lattner <sabre@nondot.org> Wed Jan 19 17:24:34 2005 +0000
committer Chris Lattner <sabre@nondot.org> Wed Jan 19 17:24:34 2005 +0000
tree 1abf83520ccd2bb56fe371ff7c15ef713f77a67b
parent 1cffa73f2a1726b82e53ec95f330ab3a07a712fd

Fix a problem where were were literally selecting for INCREASED register
pressure, not decreases register pressure.  Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail.  This fixes
fourinarow.

llvm-svn: 19697

llvm/lib/Target/X86/X86ISelPattern.cpp

diff --git a/llvm/lib/Target/X86/X86ISelPattern.cpp b/llvm/lib/Target/X86/X86ISelPattern.cpp
index 574cbf7..901077b 100644
--- a/llvm/lib/Target/X86/X86ISelPattern.cpp
+++ b/llvm/lib/Target/X86/X86ISelPattern.cpp
@@ -1185,11 +1185,11 @@
         } else if (RegSize != 8) {
           unsigned AReg, BReg;
           if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
-            AReg = SelectExpr(ShrVal);
             BReg = SelectExpr(ShlVal);
+            AReg = SelectExpr(ShrVal);
           } else {
-            BReg = SelectExpr(ShlVal);
             AReg = SelectExpr(ShrVal);
+            BReg = SelectExpr(ShlVal);
           }
           unsigned ShAmt = SelectExpr(ShrAmt);
           BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
@@ -1221,11 +1221,11 @@
         } else if (RegSize != 8) {
           unsigned AReg, BReg;
           if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
-            AReg = SelectExpr(ShrVal);
-            BReg = SelectExpr(ShlVal);
+            AReg = SelectExpr(ShlVal);
+            BReg = SelectExpr(ShrVal);
           } else {
-            BReg = SelectExpr(ShlVal);
-            AReg = SelectExpr(ShrVal);
+            BReg = SelectExpr(ShrVal);
+            AReg = SelectExpr(ShlVal);
           }
           unsigned ShAmt = SelectExpr(ShlAmt);
           BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
@@ -1250,11 +1250,11 @@
           } else if (RegSize != 8) {
             unsigned AReg, BReg;
             if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
-              AReg = SelectExpr(ShrVal);
               BReg = SelectExpr(ShlVal);
+              AReg = SelectExpr(ShrVal);
             } else {
-              BReg = SelectExpr(ShlVal);
               AReg = SelectExpr(ShrVal);
+              BReg = SelectExpr(ShlVal);
             }
             unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8;
             BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)