commit 47eb63684d22c12b9defb99c394dbd10e26fefff
author Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> Mon Dec 17 17:38:11 2018 +0000
committer Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> Mon Dec 17 17:38:11 2018 +0000
tree f497778b8180320c30d0dda8125e049f5a7d1916
parent f700c8b25378acf912982788340f4ab10d8a15ec

[AMDGPU][MC][DOC] Updated AMD GPU assembler description

Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 349368

llvm/docs/AMDGPU/gfx7_vcc_64.rst

diff --git a/llvm/docs/AMDGPU/gfx7_vcc_64.rst b/llvm/docs/AMDGPU/gfx7_vcc_64.rst
new file mode 100644
index 0000000..b1285e0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_vcc_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vcc_64:
+
+vcc
+===========================
+
+Vector condition code.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`