[llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.
This patch makes it so that cases where multiple instructions that differ only
in their FrameIndex MachineOperand values no longer collide. For instance:
%1:_(p0) = G_FRAME_INDEX %stack.0
%2:_(p0) = G_FRAME_INDEX %stack.1
Prior to this patch these instructions would collide together.
Differential Revision: https://reviews.llvm.org/D71583
diff --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
index d0670dc..fcc40b2 100644
--- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
+++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
@@ -68,6 +68,8 @@
return MO.getImm();
case MachineOperand::MO_TargetIndex:
return MO.getOffset() | (MO.getTargetFlags() << 16);
+ case MachineOperand::MO_FrameIndex:
+ return llvm::hash_value(MO);
// We could explicitly handle all the types of the MachineOperand,
// here but we can just return a common number until we find a
@@ -77,7 +79,6 @@
// TODO: Handle the following Index/ID/Predicate cases. They can
// be hashed on in a stable manner.
- case MachineOperand::MO_FrameIndex:
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_CFIIndex: