[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index bf0be8e..077f4ac 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -667,7 +667,7 @@
EmitLinkage(&F, CurrentFnSym);
if (MAI->hasFunctionAlignment())
- EmitAlignment(MF->getLogAlignment(), &F);
+ EmitAlignment(Log2(MF->getAlignment()), &F);
if (MAI->hasDotTypeDotSizeDirective())
OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_ELF_TypeFunction);
diff --git a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp
index ef5aa04..4f56177 100644
--- a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp
@@ -204,7 +204,7 @@
// We want our funclet's entry point to be aligned such that no nops will be
// present after the label.
Asm->EmitAlignment(
- std::max(Asm->MF->getLogAlignment(), MBB.getLogAlignment()), &F);
+ Log2(std::max(Asm->MF->getAlignment(), MBB.getAlignment())), &F);
// Now that we've emitted the alignment directive, point at our funclet.
Asm->OutStreamer->EmitLabel(Sym);
diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index 4ee61cf..d027d5b 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -64,19 +64,18 @@
/// Compute the offset immediately following this block. \p MBB is the next
/// block.
unsigned postOffset(const MachineBasicBlock &MBB) const {
- unsigned PO = Offset + Size;
- unsigned LogAlign = MBB.getLogAlignment();
- if (LogAlign == 0)
+ const unsigned PO = Offset + Size;
+ const llvm::Align Align = MBB.getAlignment();
+ if (Align == 1)
return PO;
- unsigned AlignAmt = 1 << LogAlign;
- unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
- if (LogAlign <= ParentLogAlign)
- return PO + OffsetToAlignment(PO, AlignAmt);
+ const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
+ if (Align <= ParentAlign)
+ return PO + OffsetToAlignment(PO, Align.value());
// The alignment of this MBB is larger than the function's alignment, so we
// can't tell whether or not it will insert nops. Assume that it will.
- return PO + AlignAmt + OffsetToAlignment(PO, AlignAmt);
+ return PO + Align.value() + OffsetToAlignment(PO, Align.value());
}
};
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 2dd4fd3..72d3d1d 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -393,7 +393,7 @@
}
if (YamlMF.Alignment)
- MF.setLogAlignment(Log2_32(YamlMF.Alignment));
+ MF.setAlignment(llvm::Align(YamlMF.Alignment));
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
MF.setHasWinCFI(YamlMF.HasWinCFI);
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 18efe1f..415f28b 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -197,7 +197,7 @@
yaml::MachineFunction YamlMF;
YamlMF.Name = MF.getName();
- YamlMF.Alignment = 1UL << MF.getLogAlignment();
+ YamlMF.Alignment = MF.getAlignment().value();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
YamlMF.HasWinCFI = MF.hasWinCFI();
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index d136ebd..832895e 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -173,16 +173,16 @@
FrameInfo->ensureMaxAlignment(F.getFnStackAlignment());
ConstantPool = new (Allocator) MachineConstantPool(getDataLayout());
- LogAlignment = STI->getTargetLowering()->getMinFunctionLogAlignment();
+ Alignment = STI->getTargetLowering()->getMinFunctionAlignment();
// FIXME: Shouldn't use pref alignment if explicit alignment is set on F.
// FIXME: Use Function::hasOptSize().
if (!F.hasFnAttribute(Attribute::OptimizeForSize))
- LogAlignment = std::max(
- LogAlignment, STI->getTargetLowering()->getPrefFunctionLogAlignment());
+ Alignment = std::max(Alignment,
+ STI->getTargetLowering()->getPrefFunctionAlignment());
if (AlignAllFunctions)
- LogAlignment = AlignAllFunctions;
+ Alignment = llvm::Align(1ULL << AlignAllFunctions);
JumpTableInfo = nullptr;
diff --git a/llvm/lib/CodeGen/PatchableFunction.cpp b/llvm/lib/CodeGen/PatchableFunction.cpp
index 07f8859..9d7605f 100644
--- a/llvm/lib/CodeGen/PatchableFunction.cpp
+++ b/llvm/lib/CodeGen/PatchableFunction.cpp
@@ -78,7 +78,7 @@
MIB.add(MO);
FirstActualI->eraseFromParent();
- MF.ensureLogAlignment(4);
+ MF.ensureAlignment(llvm::Align(16));
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 12118e6..1e3c7ed 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -417,7 +417,7 @@
// The starting address of all shader programs must be 256 bytes aligned.
// Regular functions just need the basic required instruction alignment.
- MF.setLogAlignment(MFI->isEntryFunction() ? 8 : 2);
+ MF.setAlignment(MFI->isEntryFunction() ? llvm::Align(256) : llvm::Align(4));
SetupMachineFunction(MF);
diff --git a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
index 7918f6b..4215815 100644
--- a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
@@ -104,7 +104,7 @@
// Functions needs to be cacheline (256B) aligned.
- MF.ensureLogAlignment(8);
+ MF.ensureAlignment(llvm::Align(256));
SetupMachineFunction(MF);
diff --git a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
index f59b0ae6..997327f 100644
--- a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
+++ b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
@@ -34,8 +34,8 @@
explicit ARCFunctionInfo(MachineFunction &MF)
: ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
ReturnStackOffset(-1U), MaxCallStackReq(0) {
- // Functions are 4-byte (2**2) aligned.
- MF.setLogAlignment(2);
+ // Functions are 4-byte aligned.
+ MF.setAlignment(llvm::Align(4));
}
~ARCFunctionInfo() {}
diff --git a/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp b/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp
index d8ca5fd..a8bdefa 100644
--- a/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp
@@ -63,7 +63,7 @@
// tBR_JTr contains a .align 2 directive.
if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
BBI.PostAlign = 2;
- MBB->getParent()->ensureLogAlignment(2);
+ MBB->getParent()->ensureAlignment(llvm::Align(4));
}
}
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index ae62d97..9d3e820 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -396,7 +396,7 @@
// Functions with jump tables need an alignment of 4 because they use the ADR
// instruction, which aligns the PC to 4 bytes before adding an offset.
if (!T2JumpTables.empty())
- MF->ensureLogAlignment(2);
+ MF->ensureAlignment(llvm::Align(4));
/// Remove dead constant pool entries.
MadeChange |= removeUnusedCPEntries();
@@ -493,7 +493,7 @@
// The function needs to be as aligned as the basic blocks. The linker may
// move functions around based on their alignment.
- MF->ensureLogAlignment(BB->getLogAlignment());
+ MF->ensureAlignment(BB->getAlignment());
// Order the entries in BB by descending alignment. That ensures correct
// alignment of all entries as long as BB is sufficiently aligned. Keep
@@ -686,7 +686,7 @@
BBInfoVector &BBInfo = BBUtils->getBBInfo();
// The known bits of the entry block offset are determined by the function
// alignment.
- BBInfo.front().KnownBits = MF->getLogAlignment();
+ BBInfo.front().KnownBits = Log2(MF->getAlignment());
// Compute block offsets and known bits.
BBUtils->adjustBBOffsetsAfter(&MF->front());
@@ -1041,7 +1041,8 @@
// the offset of the instruction. Also account for unknown alignment padding
// in blocks between CPE and the user.
if (CPEOffset < UserOffset)
- UserOffset += Growth + UnknownPadding(MF->getLogAlignment(), CPELogAlign);
+ UserOffset +=
+ Growth + UnknownPadding(Log2(MF->getAlignment()), CPELogAlign);
} else
// CPE fits in existing padding.
Growth = 0;
@@ -1316,7 +1317,7 @@
// Try to split the block so it's fully aligned. Compute the latest split
// point where we can add a 4-byte branch instruction, and then align to
// LogAlign which is the largest possible alignment in the function.
- unsigned LogAlign = MF->getLogAlignment();
+ unsigned LogAlign = Log2(MF->getAlignment());
assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
unsigned KnownBits = UserBBI.internalKnownBits();
unsigned UPad = UnknownPadding(LogAlign, KnownBits);
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 750d0c5..8840a49 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -400,7 +400,8 @@
// NaCl sandboxing requires that indirect call instructions are masked.
// This means that function entry points should be bundle-aligned.
if (Subtarget->isTargetNaCl())
- EmitAlignment(std::max(MF->getLogAlignment(), MIPS_NACL_BUNDLE_LOG_ALIGN));
+ EmitAlignment(
+ std::max(Log2(MF->getAlignment()), MIPS_NACL_BUNDLE_LOG_ALIGN));
if (Subtarget->inMicroMipsMode()) {
TS.emitDirectiveSetMicroMips();
diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
index 8907a72..4cd64c6 100644
--- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -542,7 +542,7 @@
// The function needs to be as aligned as the basic blocks. The linker may
// move functions around based on their alignment.
- MF->ensureLogAlignment(BB->getLogAlignment());
+ MF->ensureAlignment(BB->getAlignment());
// Order the entries in BB by descending alignment. That ensures correct
// alignment of all entries as long as BB is sufficiently aligned. Keep
@@ -1259,7 +1259,7 @@
// Try to split the block so it's fully aligned. Compute the latest split
// point where we can add a 4-byte branch instruction, and then align to
// LogAlign which is the largest possible alignment in the function.
- unsigned LogAlign = MF->getLogAlignment();
+ unsigned LogAlign = Log2(MF->getAlignment());
assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
unsigned BaseInsertOffset = UserOffset + U.getMaxDisp();
LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
index 353a348..6b95d0d 100644
--- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -81,21 +81,20 @@
/// original Offset.
unsigned PPCBSel::GetAlignmentAdjustment(MachineBasicBlock &MBB,
unsigned Offset) {
- unsigned LogAlign = MBB.getLogAlignment();
- if (!LogAlign)
+ const llvm::Align Align = MBB.getAlignment();
+ if (Align == 1)
return 0;
- unsigned AlignAmt = 1 << LogAlign;
- unsigned ParentLogAlign = MBB.getParent()->getLogAlignment();
+ const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
- if (LogAlign <= ParentLogAlign)
- return OffsetToAlignment(Offset, AlignAmt);
+ if (Align <= ParentAlign)
+ return OffsetToAlignment(Offset, Align.value());
// The alignment of this MBB is larger than the function's alignment, so we
// can't tell whether or not it will insert nops. Assume that it will.
if (FirstImpreciseBlock < 0)
FirstImpreciseBlock = MBB.getNumber();
- return AlignAmt + OffsetToAlignment(Offset, AlignAmt);
+ return Align.value() + OffsetToAlignment(Offset, Align.value());
}
/// We need to be careful about the offset of the first block in the function
diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
index 2b2c80cd..452c439 100644
--- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
@@ -276,7 +276,7 @@
Terminators.clear();
Terminators.reserve(NumBlocks);
- BlockPosition Position(MF->getLogAlignment());
+ BlockPosition Position(Log2(MF->getAlignment()));
for (unsigned I = 0; I < NumBlocks; ++I) {
MachineBasicBlock *MBB = MF->getBlockNumbered(I);
MBBInfo &Block = MBBs[I];
@@ -340,7 +340,7 @@
// must be long.
void SystemZLongBranch::setWorstCaseAddresses() {
SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
- BlockPosition Position(MF->getLogAlignment());
+ BlockPosition Position(Log2(MF->getAlignment()));
for (auto &Block : MBBs) {
skipNonTerminators(Position, Block);
for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
@@ -441,7 +441,7 @@
// Run a shortening pass and relax any branches that need to be relaxed.
void SystemZLongBranch::relaxBranches() {
SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
- BlockPosition Position(MF->getLogAlignment());
+ BlockPosition Position(Log2(MF->getAlignment()));
for (auto &Block : MBBs) {
skipNonTerminators(Position, Block);
for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {