Revert "[DebugInfo] Add debug locations to constant SD nodes"
This breaks a test:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870
llvm-svn: 235987
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 7a213aa..d02c6ee 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -108,24 +108,24 @@
// XformMskToBitPosU5Imm - Returns the bit position which
// the single bit 32 bit mask represents.
// Used in Clr and Set bit immediate memops.
- SDValue XformMskToBitPosU5Imm(uint32_t Imm, SDLoc DL) {
+ SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
int32_t bitPos;
bitPos = Log2_32(Imm);
assert(bitPos >= 0 && bitPos < 32 &&
"Constant out of range for 32 BitPos Memops");
- return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
+ return CurDAG->getTargetConstant(bitPos, MVT::i32);
}
// XformMskToBitPosU4Imm - Returns the bit position which the single-bit
// 16 bit mask represents. Used in Clr and Set bit immediate memops.
- SDValue XformMskToBitPosU4Imm(uint16_t Imm, SDLoc DL) {
- return XformMskToBitPosU5Imm(Imm, DL);
+ SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
+ return XformMskToBitPosU5Imm(Imm);
}
// XformMskToBitPosU3Imm - Returns the bit position which the single-bit
// 8 bit mask represents. Used in Clr and Set bit immediate memops.
- SDValue XformMskToBitPosU3Imm(uint8_t Imm, SDLoc DL) {
- return XformMskToBitPosU5Imm(Imm, DL);
+ SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
+ return XformMskToBitPosU5Imm(Imm);
}
// Return true if there is exactly one bit set in V, i.e., if V is one of the
@@ -137,37 +137,37 @@
// XformM5ToU5Imm - Return a target constant with the specified value, of
// type i32 where the negative literal is transformed into a positive literal
// for use in -= memops.
- inline SDValue XformM5ToU5Imm(signed Imm, SDLoc DL) {
+ inline SDValue XformM5ToU5Imm(signed Imm) {
assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
- return CurDAG->getTargetConstant( - Imm, DL, MVT::i32);
+ return CurDAG->getTargetConstant( - Imm, MVT::i32);
}
// XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
// [1..128], used in cmpb.gtu instructions.
- inline SDValue XformU7ToU7M1Imm(signed Imm, SDLoc DL) {
+ inline SDValue XformU7ToU7M1Imm(signed Imm) {
assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
- return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8);
+ return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
}
// XformS8ToS8M1Imm - Return a target constant decremented by 1.
- inline SDValue XformSToSM1Imm(signed Imm, SDLoc DL) {
- return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
+ inline SDValue XformSToSM1Imm(signed Imm) {
+ return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
}
// XformU8ToU8M1Imm - Return a target constant decremented by 1.
- inline SDValue XformUToUM1Imm(unsigned Imm, SDLoc DL) {
+ inline SDValue XformUToUM1Imm(unsigned Imm) {
assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
- return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
+ return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
}
// XformSToSM2Imm - Return a target constant decremented by 2.
- inline SDValue XformSToSM2Imm(unsigned Imm, SDLoc DL) {
- return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32);
+ inline SDValue XformSToSM2Imm(unsigned Imm) {
+ return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
}
// XformSToSM3Imm - Return a target constant decremented by 3.
- inline SDValue XformSToSM3Imm(unsigned Imm, SDLoc DL) {
- return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32);
+ inline SDValue XformSToSM3Imm(unsigned Imm) {
+ return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
}
// Include the pieces autogenerated from the target description.
@@ -259,7 +259,7 @@
const HexagonInstrInfo &TII = *HST->getInstrInfo();
if (TII.isValidAutoIncImm(LoadedVT, Val)) {
- SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32);
+ SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
MVT::Other, Base, TargetConst,
Chain);
@@ -278,8 +278,8 @@
return Result_2;
}
- SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
- SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
+ SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
+ SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
Base, TargetConst0, Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
@@ -313,8 +313,8 @@
const HexagonInstrInfo &TII = *HST->getInstrInfo();
if (TII.isValidAutoIncImm(LoadedVT, Val)) {
- SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
- SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
+ SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
+ SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::i32, MVT::Other, Base,
TargetConstVal, Chain);
@@ -336,8 +336,8 @@
}
// Generate an indirect load.
- SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
- SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
+ SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
+ SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::Other, Base, TargetConst0,
Chain);
@@ -411,7 +411,7 @@
return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
if (TII.isValidAutoIncImm(LoadedVT, Val)) {
- SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
+ SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
LD->getValueType(0),
MVT::i32, MVT::Other, Base,
@@ -430,8 +430,8 @@
ReplaceUses(Froms, Tos, 3);
return Result;
} else {
- SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
- SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
+ SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
+ SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
LD->getValueType(0),
MVT::Other, Base, TargetConst0,
@@ -502,7 +502,7 @@
Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
dl, MVT::i32, Value);
}
- SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl, MVT::i32), Value,
+ SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
Chain};
// Build post increment store.
SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
@@ -520,7 +520,7 @@
// def S2_storerd_io
// : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
// and it differs for POST_ST* for instance.
- SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl, MVT::i32), Value,
+ SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
Chain};
unsigned Opcode = 0;
@@ -532,7 +532,7 @@
else llvm_unreachable("unknown memory type");
// Build regular store.
- SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
+ SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
// Build splitted incriment instruction.
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
@@ -599,7 +599,7 @@
}
SDValue Chain = LD->getChain();
- SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
+ SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other,
LD->getBasePtr(), TargetConst0,
@@ -625,7 +625,7 @@
}
SDValue Chain = LD->getChain();
- SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
+ SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other,
LD->getBasePtr(), TargetConst0,
@@ -661,7 +661,7 @@
int32_t MulConst =
cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
int32_t ValConst = MulConst << ShlConst;
- SDValue Val = CurDAG->getTargetConstant(ValConst, dl,
+ SDValue Val = CurDAG->getTargetConstant(ValConst,
MVT::i32);
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
if (isInt<9>(CN->getSExtValue())) {
@@ -689,8 +689,7 @@
int32_t Shl2Const =
cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
int32_t ValConst = 1 << (ShlConst+Shl2Const);
- SDValue Val = CurDAG->getTargetConstant(-ValConst, dl,
- MVT::i32);
+ SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
if (ConstantSDNode *CN =
dyn_cast<ConstantSDNode>(Val.getNode()))
if (isInt<9>(CN->getSExtValue())) {
@@ -739,14 +738,13 @@
MV |= Bit;
Bit <<= ES;
}
- SDValue Ones = CurDAG->getTargetConstant(MV, dl, MVT::i64);
+ SDValue Ones = CurDAG->getTargetConstant(MV, MVT::i64);
SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
MVT::i64, Ones);
if (ExVT.getSizeInBits() == 32) {
SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
SDValue(Mask,0), SDValue(OnesReg,0));
- SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
- MVT::i32);
+ SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, MVT::i32);
return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
SDValue(And,0), SubR);
}
@@ -762,7 +760,7 @@
// Now we need to differentiate target data types.
if (N->getValueType(0) == MVT::i64) {
// Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
- SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
+ SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
MVT::i32,
SDValue(IsIntrinsic, 0));
@@ -869,7 +867,7 @@
Ops.push_back(Load);
Ops.push_back(ModifierExpr);
int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
- Ops.push_back(CurDAG->getTargetConstant(Val, dl, MVT::i32));
+ Ops.push_back(CurDAG->getTargetConstant(Val, MVT::i32));
Ops.push_back(Chain);
SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
@@ -1024,11 +1022,11 @@
APFloat APF = CN->getValueAPF();
if (N->getValueType(0) == MVT::f32) {
return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
- CurDAG->getTargetConstantFP(APF.convertToFloat(), dl, MVT::f32));
+ CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
}
else if (N->getValueType(0) == MVT::f64) {
return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
- CurDAG->getTargetConstantFP(APF.convertToDouble(), dl, MVT::f64));
+ CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
}
return SelectCode(N);
@@ -1168,7 +1166,7 @@
SDNode *Result;
// Get the right SDVal for the opcode.
- SDValue SDVal = CurDAG->getTargetConstant(bitpos, dl, MVT::i32);
+ SDValue SDVal = CurDAG->getTargetConstant(bitpos, MVT::i32);
if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
@@ -1183,11 +1181,11 @@
SDNode *Reg = N->getOperand(0).getNode();
SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
- dl, MVT::i64);
+ MVT::i64);
- SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl,
+ SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg,
MVT::i32);
- SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
+ SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg,
MVT::i32);
SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
@@ -1206,7 +1204,7 @@
dl, ValueVT, Ops);
} else {
if (Opc != ISD::FABS && Opc != ISD::FNEG)
- SDVal = CurDAG->getTargetConstant(bitpos - 32, dl, MVT::i32);
+ SDVal = CurDAG->getTargetConstant(bitpos-32, MVT::i32);
SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
SubregHI, SDVal);
const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
@@ -1228,8 +1226,8 @@
unsigned StkA = HFI->getStackAlignment();
unsigned MaxA = MFI->getMaxAlignment();
SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
+ SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
SDLoc DL(N);
- SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
SDNode *R = 0;
// Use TFR_FI when:
@@ -1323,7 +1321,7 @@
break;
}
- OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
+ OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 22a6ed7..86fb06a 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -344,7 +344,7 @@
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
SDLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*isVolatile=*/false, /*AlwaysInline=*/false,
/*isTailCall=*/false,
@@ -542,8 +542,7 @@
if (VA.isMemLoc()) {
unsigned LocMemOffset = VA.getLocMemOffset();
- SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
- StackPtr.getValueType());
+ SDValue MemAddr = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
if (Flags.isByVal()) {
// The argument is a struct passed by value. According to LLVM, "Arg"
@@ -571,7 +570,7 @@
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
if (!isTailCall) {
- SDValue C = DAG.getConstant(NumBytes, dl, getPointerTy(), true);
+ SDValue C = DAG.getConstant(NumBytes, getPointerTy(), true);
Chain = DAG.getCALLSEQ_START(Chain, C, dl);
}
@@ -645,8 +644,8 @@
InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node.
- Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
- DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), InFlag, dl);
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
@@ -809,7 +808,7 @@
SDValue JumpTableBase = DAG.getNode(HexagonISD::JT, dl,
getPointerTy(), TargetJT);
SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
- DAG.getConstant(2, dl, MVT::i32));
+ DAG.getConstant(2, MVT::i32));
SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
ShiftIndex);
SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
@@ -842,7 +841,7 @@
dbgs() << "\n";
});
- SDValue AC = DAG.getConstant(A, dl, MVT::i32);
+ SDValue AC = DAG.getConstant(A, MVT::i32);
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
return DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
}
@@ -995,7 +994,7 @@
SDValue InpVal = Op.getOperand(0);
if (isa<ConstantSDNode>(InpVal)) {
uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
- return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
+ return DAG.getTargetConstant(countPopulation(V), MVT::i64);
}
SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
@@ -1096,7 +1095,7 @@
LoadNode->isInvariant(),
Alignment);
// Base+2 load.
- SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
+ SDValue Increment = DAG.getConstant(2, MVT::i32);
Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
LoadNode->getPointerInfo(), MVT::i16,
@@ -1105,11 +1104,11 @@
LoadNode->isInvariant(),
Alignment);
// SHL 16, then OR base and base+2.
- SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
+ SDValue ShiftAmount = DAG.getConstant(16, MVT::i32);
SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
// Base + 4.
- Increment = DAG.getConstant(4, DL, MVT::i32);
+ Increment = DAG.getConstant(4, MVT::i32);
Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
LoadNode->getPointerInfo(), MVT::i16,
@@ -1118,7 +1117,7 @@
LoadNode->isInvariant(),
Alignment);
// Base + 6.
- Increment = DAG.getConstant(6, DL, MVT::i32);
+ Increment = DAG.getConstant(6, MVT::i32);
Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
LoadNode->getPointerInfo(), MVT::i16,
@@ -1184,7 +1183,7 @@
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
if (Depth) {
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
- SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
+ SDValue Offset = DAG.getConstant(4, MVT::i32);
return DAG.getLoad(VT, dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
MachinePointerInfo(), false, false, false, 0);
@@ -1823,7 +1822,7 @@
if (IsScalarToVector)
return createSplat(DAG, dl, VT, V1.getOperand(0));
}
- return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
+ return createSplat(DAG, dl, VT, DAG.getConstant(Lane, MVT::i32));
}
// FIXME: We need to support more general vector shuffles. See
@@ -1931,7 +1930,7 @@
unsigned SplatBits = APSplatBits.getZExtValue();
int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
(32 - SplatBitSize));
- return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
+ return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, MVT::i32));
}
// Try to generate COMBINE to build v2i32 vectors.
@@ -1940,9 +1939,9 @@
SDValue V1 = BVN->getOperand(1);
if (V0.getOpcode() == ISD::UNDEF)
- V0 = DAG.getConstant(0, dl, MVT::i32);
+ V0 = DAG.getConstant(0, MVT::i32);
if (V1.getOpcode() == ISD::UNDEF)
- V1 = DAG.getConstant(0, dl, MVT::i32);
+ V1 = DAG.getConstant(0, MVT::i32);
ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
@@ -2003,17 +2002,17 @@
}
if (Size == 64)
- ConstVal = DAG.getConstant(Res, dl, MVT::i64);
+ ConstVal = DAG.getConstant(Res, MVT::i64);
else
- ConstVal = DAG.getConstant(Res, dl, MVT::i32);
+ ConstVal = DAG.getConstant(Res, MVT::i32);
// When there are non constant operands, add them with INSERT_VECTOR_ELT to
// ConstVal, the constant part of the vector.
if (HasNonConstantElements) {
EVT EltVT = VT.getVectorElementType();
- SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
+ SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), MVT::i64);
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
- DAG.getConstant(32, dl, MVT::i64));
+ DAG.getConstant(32, MVT::i64));
for (unsigned i = 0, e = NElts; i != e; ++i) {
// LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
@@ -2026,11 +2025,11 @@
if (VT.getSizeInBits() == 64 &&
Operand.getValueType().getSizeInBits() == 32) {
- SDValue C = DAG.getConstant(0, dl, MVT::i32);
+ SDValue C = DAG.getConstant(0, MVT::i32);
Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
}
- SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
+ SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
const SDValue Ops[] = {ConstVal, Operand, Combined};
@@ -2053,10 +2052,10 @@
unsigned NElts = Op.getNumOperands();
SDValue Vec = Op.getOperand(0);
EVT VecVT = Vec.getValueType();
- SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), dl, MVT::i64);
+ SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), MVT::i64);
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
- DAG.getConstant(32, dl, MVT::i64));
- SDValue ConstVal = DAG.getConstant(0, dl, MVT::i64);
+ DAG.getConstant(32, MVT::i64));
+ SDValue ConstVal = DAG.getConstant(0, MVT::i64);
ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width);
ConstantSDNode *S = dyn_cast<ConstantSDNode>(Shifted);
@@ -2085,11 +2084,11 @@
if (VT.getSizeInBits() == 64 &&
Operand.getValueType().getSizeInBits() == 32) {
- SDValue C = DAG.getConstant(0, dl, MVT::i32);
+ SDValue C = DAG.getConstant(0, MVT::i32);
Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
}
- SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
+ SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
const SDValue Ops[] = {ConstVal, Operand, Combined};
@@ -2115,12 +2114,12 @@
EVT EltVT = VecVT.getVectorElementType();
int EltSize = EltVT.getSizeInBits();
SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
- EltSize : VTN * EltSize, dl, MVT::i64);
+ EltSize : VTN * EltSize, MVT::i64);
// Constant element number.
if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
uint64_t X = CI->getZExtValue();
- SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
+ SDValue Offset = DAG.getConstant(X * EltSize, MVT::i32);
const SDValue Ops[] = {Vec, Width, Offset};
ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
@@ -2159,9 +2158,9 @@
// Variable element number.
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
- DAG.getConstant(EltSize, dl, MVT::i32));
+ DAG.getConstant(EltSize, MVT::i32));
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
- DAG.getConstant(32, dl, MVT::i64));
+ DAG.getConstant(32, MVT::i64));
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
const SDValue Ops[] = {Vec, Combined};
@@ -2190,10 +2189,10 @@
EVT EltVT = VecVT.getVectorElementType();
int EltSize = EltVT.getSizeInBits();
SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
- EltSize : VTN * EltSize, dl, MVT::i64);
+ EltSize : VTN * EltSize, MVT::i64);
if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
- SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
+ SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, MVT::i32);
const SDValue Ops[] = {Vec, Val, Width, Offset};
SDValue N;
@@ -2207,14 +2206,14 @@
// Variable element number.
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
- DAG.getConstant(EltSize, dl, MVT::i32));
+ DAG.getConstant(EltSize, MVT::i32));
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
- DAG.getConstant(32, dl, MVT::i64));
+ DAG.getConstant(32, MVT::i64));
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
if (VT.getSizeInBits() == 64 &&
Val.getValueType().getSizeInBits() == 32) {
- SDValue C = DAG.getConstant(0, dl, MVT::i32);
+ SDValue C = DAG.getConstant(0, MVT::i32);
Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
}
@@ -2258,7 +2257,7 @@
SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
DAG.getRegister(Hexagon::R30, getPointerTy()),
- DAG.getIntPtrConstant(4, dl));
+ DAG.getIntPtrConstant(4));
Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
false, false, 0);
Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 3b32c10..6df811e 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -36,28 +36,28 @@
def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
int32_t imm = N->getSExtValue();
- return XformSToSM1Imm(imm, SDLoc(N));
+ return XformSToSM1Imm(imm);
}]>;
// SDNode for converting immediate C to C-2.
def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-2 as an SDNode.
int32_t imm = N->getSExtValue();
- return XformSToSM2Imm(imm, SDLoc(N));
+ return XformSToSM2Imm(imm);
}]>;
// SDNode for converting immediate C to C-3.
def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-3 as an SDNode.
int32_t imm = N->getSExtValue();
- return XformSToSM3Imm(imm, SDLoc(N));
+ return XformSToSM3Imm(imm);
}]>;
// SDNode for converting immediate C to C-1.
def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
uint32_t imm = N->getZExtValue();
- return XformUToUM1Imm(imm, SDLoc(N));
+ return XformUToUM1Imm(imm);
}]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
index 8b667c6..ecfde17 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -57,7 +57,7 @@
// Return the bit position we will set [0-31].
// As an SDNode.
int32_t imm = N->getSExtValue();
- return XformMskToBitPosU5Imm(imm, SDLoc(N));
+ return XformMskToBitPosU5Imm(imm);
}]>;
@@ -1153,14 +1153,14 @@
// -1 etc is represented as 255 etc
// assigning to a byte restores our desired signed value.
int8_t imm = N->getSExtValue();
- return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
+ return CurDAG->getTargetConstant(imm, MVT::i32);
}]>;
def IMM_HALF : SDNodeXForm<imm, [{
// -1 etc is represented as 65535 etc
// assigning to a short restores our desired signed value.
int16_t imm = N->getSExtValue();
- return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
+ return CurDAG->getTargetConstant(imm, MVT::i32);
}]>;
def IMM_WORD : SDNodeXForm<imm, [{
@@ -1169,7 +1169,7 @@
// might convert -1 to a large +ve number.
// assigning to a word restores our desired signed value.
int32_t imm = N->getSExtValue();
- return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
+ return CurDAG->getTargetConstant(imm, MVT::i32);
}]>;
def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
@@ -2805,7 +2805,7 @@
// Call the transformation function XformM5ToU5Imm to get the negative
// immediate's positive counterpart.
int32_t imm = N->getSExtValue();
- return XformM5ToU5Imm(imm, SDLoc(N));
+ return XformM5ToU5Imm(imm);
}]>;
def MEMOPIMM_HALF : SDNodeXForm<imm, [{
@@ -2814,7 +2814,7 @@
// Call the transformation function XformM5ToU5Imm to get the negative
// immediate's positive counterpart.
int16_t imm = N->getSExtValue();
- return XformM5ToU5Imm(imm, SDLoc(N));
+ return XformM5ToU5Imm(imm);
}]>;
def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
@@ -2823,14 +2823,14 @@
// Call the transformation function XformM5ToU5Imm to get the negative
// immediate's positive counterpart.
int8_t imm = N->getSExtValue();
- return XformM5ToU5Imm(imm, SDLoc(N));
+ return XformM5ToU5Imm(imm);
}]>;
def SETMEMIMM : SDNodeXForm<imm, [{
// Return the bit position we will set [0-31].
// As an SDNode.
int32_t imm = N->getSExtValue();
- return XformMskToBitPosU5Imm(imm, SDLoc(N));
+ return XformMskToBitPosU5Imm(imm);
}]>;
def CLRMEMIMM : SDNodeXForm<imm, [{
@@ -2838,14 +2838,14 @@
// As an SDNode.
// we bit negate the value first
int32_t imm = ~(N->getSExtValue());
- return XformMskToBitPosU5Imm(imm, SDLoc(N));
+ return XformMskToBitPosU5Imm(imm);
}]>;
def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
// Return the bit position we will set [0-15].
// As an SDNode.
int16_t imm = N->getSExtValue();
- return XformMskToBitPosU4Imm(imm, SDLoc(N));
+ return XformMskToBitPosU4Imm(imm);
}]>;
def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
@@ -2853,14 +2853,14 @@
// As an SDNode.
// we bit negate the value first
int16_t imm = ~(N->getSExtValue());
- return XformMskToBitPosU4Imm(imm, SDLoc(N));
+ return XformMskToBitPosU4Imm(imm);
}]>;
def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
// Return the bit position we will set [0-7].
// As an SDNode.
int8_t imm = N->getSExtValue();
- return XformMskToBitPosU3Imm(imm, SDLoc(N));
+ return XformMskToBitPosU3Imm(imm);
}]>;
def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
@@ -2868,7 +2868,7 @@
// As an SDNode.
// we bit negate the value first
int8_t imm = ~(N->getSExtValue());
- return XformMskToBitPosU3Imm(imm, SDLoc(N));
+ return XformMskToBitPosU3Imm(imm);
}]>;
//===----------------------------------------------------------------------===//
@@ -3202,7 +3202,7 @@
def DEC_CONST_BYTE : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
int32_t imm = N->getSExtValue();
- return XformU7ToU7M1Imm(imm, SDLoc(N));
+ return XformU7ToU7M1Imm(imm);
}]>;
// For the sequence