Revert "[DebugInfo] Add debug locations to constant SD nodes"
This breaks a test:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870
llvm-svn: 235987
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
index 7b6a2a1..3221ccb 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -163,15 +163,14 @@
bool Mips16DAGToDAGISel::selectAddr16(
SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
SDValue &Alias) {
- SDLoc DL(Addr);
EVT ValTy = Addr.getValueType();
- Alias = CurDAG->getTargetConstant(0, DL, ValTy);
+ Alias = CurDAG->getTargetConstant(0, ValTy);
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
- Offset = CurDAG->getTargetConstant(0, DL, ValTy);
+ Offset = CurDAG->getTargetConstant(0, ValTy);
getMips16SPRefReg(Parent, Alias);
return true;
}
@@ -200,7 +199,7 @@
else
Base = Addr.getOperand(0);
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), DL, ValTy);
+ Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
return true;
}
}
@@ -236,7 +235,7 @@
}
}
Base = Addr;
- Offset = CurDAG->getTargetConstant(0, DL, ValTy);
+ Offset = CurDAG->getTargetConstant(0, ValTy);
return true;
}
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
index 7096a52..aec731e 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -119,7 +119,7 @@
// getImm - Return a target constant with the specified value.
inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0));
+ return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
}
virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 92abe0e..c78b79f 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -544,7 +544,7 @@
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
- DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
+ DAG.getConstant(condCodeToFCC(CC), MVT::i32));
}
// Creates and returns a CMovFPT/F node.
@@ -699,11 +699,9 @@
if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
return SDValue();
- SDLoc DL(N);
- return DAG.getNode(MipsISD::Ext, DL, ValTy,
- ShiftRight.getOperand(0),
- DAG.getConstant(Pos, DL, MVT::i32),
- DAG.getConstant(SMSize, DL, MVT::i32));
+ return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
+ ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
+ DAG.getConstant(SMSize, MVT::i32));
}
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
@@ -755,11 +753,9 @@
if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
return SDValue();
- SDLoc DL(N);
- return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
- DAG.getConstant(SMPos0, DL, MVT::i32),
- DAG.getConstant(SMSize0, DL, MVT::i32),
- And0.getOperand(0));
+ return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
+ DAG.getConstant(SMPos0, MVT::i32),
+ DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
}
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
@@ -1560,7 +1556,7 @@
DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
- DAG.getConstant(EntrySize, DL, PTy));
+ DAG.getConstant(EntrySize, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
@@ -1598,7 +1594,7 @@
Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
- SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
+ SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
FCC0, Dest, CondRes);
@@ -1639,11 +1635,10 @@
assert(Cond.getOpcode() == MipsISD::FPCmp &&
"Floating point operand expected.");
- SDLoc DL(Op);
- SDValue True = DAG.getConstant(1, DL, MVT::i32);
- SDValue False = DAG.getConstant(0, DL, MVT::i32);
+ SDValue True = DAG.getConstant(1, MVT::i32);
+ SDValue False = DAG.getConstant(0, MVT::i32);
- return createCMovFP(DAG, Cond, True, False, DL);
+ return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
}
SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
@@ -1842,19 +1837,19 @@
assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
- DAG.getConstant(Align - 1, DL, VAList.getValueType()));
+ DAG.getConstant(Align - 1,
+ VAList.getValueType()));
VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
- DAG.getConstant(-(int64_t)Align, DL,
+ DAG.getConstant(-(int64_t)Align,
VAList.getValueType()));
}
// Increment the pointer, VAList, to the next vaarg.
unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
- DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes,
- ArgSlotSizeInBytes),
- DL, VAList.getValueType()));
+ DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
+ VAList.getValueType()));
// Store the incremented VAList to the legalized pointer
Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
MachinePointerInfo(SV), false, false, 0);
@@ -1867,7 +1862,7 @@
if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
- DAG.getIntPtrConstant(Adjustment, DL));
+ DAG.getIntPtrConstant(Adjustment));
}
// Load the actual argument out of the pointer VAList
return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
@@ -1878,9 +1873,9 @@
bool HasExtractInsert) {
EVT TyX = Op.getOperand(0).getValueType();
EVT TyY = Op.getOperand(1).getValueType();
+ SDValue Const1 = DAG.getConstant(1, MVT::i32);
+ SDValue Const31 = DAG.getConstant(31, MVT::i32);
SDLoc DL(Op);
- SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
- SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
SDValue Res;
// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
@@ -1916,8 +1911,7 @@
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
- Op.getOperand(0),
- DAG.getConstant(0, DL, MVT::i32));
+ Op.getOperand(0), DAG.getConstant(0, MVT::i32));
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
}
@@ -1926,8 +1920,8 @@
unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
+ SDValue Const1 = DAG.getConstant(1, MVT::i32);
SDLoc DL(Op);
- SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
// Bitcast to integer nodes.
SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
@@ -1937,7 +1931,7 @@
// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
- DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
+ DAG.getConstant(WidthY - 1, MVT::i32), Const1);
if (WidthX > WidthY)
E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
@@ -1945,8 +1939,7 @@
E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
- DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
- X);
+ DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
}
@@ -1958,7 +1951,7 @@
SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
- DAG.getConstant(WidthY - 1, DL, MVT::i32));
+ DAG.getConstant(WidthY - 1, MVT::i32));
if (WidthX > WidthY)
SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
@@ -1966,7 +1959,7 @@
SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
- DAG.getConstant(WidthX - 1, DL, MVT::i32));
+ DAG.getConstant(WidthX - 1, MVT::i32));
SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
}
@@ -2049,7 +2042,7 @@
unsigned SType = 0;
SDLoc DL(Op);
return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
- DAG.getConstant(SType, DL, MVT::i32));
+ DAG.getConstant(SType, MVT::i32));
}
SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
@@ -2066,17 +2059,17 @@
// lo = 0
// hi = (shl lo, shamt[4:0])
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
- DAG.getConstant(-1, DL, MVT::i32));
+ DAG.getConstant(-1, MVT::i32));
SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
- DAG.getConstant(1, DL, VT));
+ DAG.getConstant(1, VT));
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
- DAG.getConstant(0x20, DL, MVT::i32));
+ DAG.getConstant(0x20, MVT::i32));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
- DAG.getConstant(0, DL, VT), ShiftLeftLo);
+ DAG.getConstant(0, VT), ShiftLeftLo);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
SDValue Ops[2] = {Lo, Hi};
@@ -2104,21 +2097,20 @@
// lo = (srl hi, shamt[4:0])
// hi = 0
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
- DAG.getConstant(-1, DL, MVT::i32));
+ DAG.getConstant(-1, MVT::i32));
SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
- DAG.getConstant(1, DL, VT));
+ DAG.getConstant(1, VT));
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
DL, VT, Hi, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
- DAG.getConstant(0x20, DL, MVT::i32));
- SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi,
- DAG.getConstant(31, DL, VT));
+ DAG.getConstant(0x20, MVT::i32));
+ SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
- IsSRA ? Shift31 : DAG.getConstant(0, DL, VT), ShiftRightHi);
+ IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
SDValue Ops[2] = {Lo, Hi};
return DAG.getMergeValues(Ops, DL);
@@ -2134,7 +2126,7 @@
if (Offset)
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
- DAG.getConstant(Offset, DL, BasePtrVT));
+ DAG.getConstant(Offset, BasePtrVT));
SDValue Ops[] = { Chain, Ptr, Src };
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
@@ -2199,7 +2191,7 @@
// (set tmp2, (shl tmp1, 32))
// (set dst, (srl tmp2, 32))
SDLoc DL(LD);
- SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
+ SDValue Const32 = DAG.getConstant(32, MVT::i32);
SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
SDValue Ops[] = { SRL, LWR.getValue(1) };
@@ -2215,7 +2207,7 @@
if (Offset)
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
- DAG.getConstant(Offset, DL, BasePtrVT));
+ DAG.getConstant(Offset, BasePtrVT));
SDValue Ops[] = { Chain, Value, Ptr };
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
@@ -2297,9 +2289,8 @@
EVT ValTy = Op->getValueType(0);
int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
- SDLoc DL(Op);
- return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
- DAG.getConstant(0, DL, ValTy));
+ return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
+ DAG.getConstant(0, ValTy));
}
SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
@@ -2456,7 +2447,7 @@
bool IsTailCall, SelectionDAG &DAG) const {
if (!IsTailCall) {
SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
- DAG.getIntPtrConstant(Offset, DL));
+ DAG.getIntPtrConstant(Offset));
return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
false, 0);
}
@@ -2582,7 +2573,7 @@
// byval arguments to the stack.
unsigned StackAlignment = TFL->getStackAlignment();
NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
- SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
+ SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
if (!IsTailCall)
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
@@ -2634,9 +2625,9 @@
Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
- Arg, DAG.getConstant(0, DL, MVT::i32));
+ Arg, DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
- Arg, DAG.getConstant(1, DL, MVT::i32));
+ Arg, DAG.getConstant(1, MVT::i32));
if (!Subtarget.isLittle())
std::swap(Lo, Hi);
unsigned LocRegLo = VA.getLocReg();
@@ -2675,7 +2666,7 @@
unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
Arg = DAG.getNode(
ISD::SHL, DL, VA.getLocVT(), Arg,
- DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
+ DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
}
// Arguments that can be passed on register must be kept at
@@ -2764,7 +2755,7 @@
// Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
- DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
+ DAG.getIntPtrConstant(0, true), InFlag, DL);
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
@@ -2803,7 +2794,7 @@
VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
Val = DAG.getNode(
Shift, DL, VA.getLocVT(), Val,
- DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
+ DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
}
switch (VA.getLocInfo()) {
@@ -2856,7 +2847,7 @@
VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
Val = DAG.getNode(
Opcode, DL, VA.getLocVT(), Val,
- DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
+ DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
break;
}
}
@@ -3130,7 +3121,7 @@
unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
Val = DAG.getNode(
ISD::SHL, DL, VA.getLocVT(), Val,
- DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
+ DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
}
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
@@ -3432,7 +3423,6 @@
std::string &Constraint,
std::vector<SDValue>&Ops,
SelectionDAG &DAG) const {
- SDLoc DL(Op);
SDValue Result;
// Only support length 1 constraints for now.
@@ -3447,7 +3437,7 @@
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if (isInt<16>(Val)) {
- Result = DAG.getTargetConstant(Val, DL, Type);
+ Result = DAG.getTargetConstant(Val, Type);
break;
}
}
@@ -3457,7 +3447,7 @@
EVT Type = Op.getValueType();
int64_t Val = C->getZExtValue();
if (Val == 0) {
- Result = DAG.getTargetConstant(0, DL, Type);
+ Result = DAG.getTargetConstant(0, Type);
break;
}
}
@@ -3467,7 +3457,7 @@
EVT Type = Op.getValueType();
uint64_t Val = (uint64_t)C->getZExtValue();
if (isUInt<16>(Val)) {
- Result = DAG.getTargetConstant(Val, DL, Type);
+ Result = DAG.getTargetConstant(Val, Type);
break;
}
}
@@ -3477,7 +3467,7 @@
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
- Result = DAG.getTargetConstant(Val, DL, Type);
+ Result = DAG.getTargetConstant(Val, Type);
break;
}
}
@@ -3487,7 +3477,7 @@
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((Val >= -65535) && (Val <= -1)) {
- Result = DAG.getTargetConstant(Val, DL, Type);
+ Result = DAG.getTargetConstant(Val, Type);
break;
}
}
@@ -3497,7 +3487,7 @@
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((isInt<15>(Val))) {
- Result = DAG.getTargetConstant(Val, DL, Type);
+ Result = DAG.getTargetConstant(Val, Type);
break;
}
}
@@ -3507,7 +3497,7 @@
EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue();
if ((Val <= 65535) && (Val >= 1)) {
- Result = DAG.getTargetConstant(Val, DL, Type);
+ Result = DAG.getTargetConstant(Val, Type);
break;
}
}
@@ -3613,7 +3603,7 @@
unsigned VReg = addLiveIn(MF, ArgReg, RC);
unsigned Offset = I * GPRSizeInBytes;
SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
- DAG.getConstant(Offset, DL, PtrTy));
+ DAG.getConstant(Offset, PtrTy));
SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
StorePtr, MachinePointerInfo(FuncArg, Offset),
false, false, 0);
@@ -3644,7 +3634,7 @@
// Copy words to registers.
for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
- DAG.getConstant(OffsetInBytes, DL, PtrTy));
+ DAG.getConstant(OffsetInBytes, PtrTy));
SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
MachinePointerInfo(), false, false, false,
Alignment);
@@ -3670,8 +3660,7 @@
// Load subword.
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
- DAG.getConstant(OffsetInBytes, DL,
- PtrTy));
+ DAG.getConstant(OffsetInBytes, PtrTy));
SDValue LoadVal = DAG.getExtLoad(
ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
@@ -3687,7 +3676,7 @@
Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
- DAG.getConstant(Shamt, DL, MVT::i32));
+ DAG.getConstant(Shamt, MVT::i32));
if (Val.getNode())
Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
@@ -3708,11 +3697,10 @@
// Copy remainder of byval arg to it with memcpy.
unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
- DAG.getConstant(OffsetInBytes, DL, PtrTy));
+ DAG.getConstant(OffsetInBytes, PtrTy));
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
- DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
- Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
- DAG.getConstant(MemCpySize, DL, PtrTy),
+ DAG.getIntPtrConstant(VA.getLocMemOffset()));
+ Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
/*isTailCall=*/false,
MachinePointerInfo(), MachinePointerInfo());
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index fe9c13f..6daa632 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -253,10 +253,9 @@
// that SLTu64 produces an i32. We need to fix this in the long run but for
// now, just make the DAG type-correct by asserting the upper bits are zero.
Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
- CurDAG->getTargetConstant(0, DL, VT),
+ CurDAG->getTargetConstant(0, VT),
SDValue(Carry, 0),
- CurDAG->getTargetConstant(Mips::sub_32, DL,
- VT));
+ CurDAG->getTargetConstant(Mips::sub_32, VT));
}
// Generate a second addition only if we know that RHS is not a
@@ -277,7 +276,7 @@
EVT ValTy = Addr.getValueType();
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
- Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
+ Offset = CurDAG->getTargetConstant(0, ValTy);
return true;
}
return false;
@@ -299,8 +298,7 @@
else
Base = Addr.getOperand(0);
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
- ValTy);
+ Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
return true;
}
}
@@ -374,7 +372,7 @@
bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const {
Base = Addr;
- Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
+ Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
return true;
}
@@ -525,7 +523,7 @@
ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
(!Signed && ImmValue.isIntN(ImmBitSize))) {
- Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
+ Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
return true;
}
}
@@ -601,7 +599,7 @@
int32_t Log2 = ImmValue.exactLogBase2();
if (Log2 != -1) {
- Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
+ Imm = CurDAG->getTargetConstant(Log2, EltTy);
return true;
}
}
@@ -634,8 +632,7 @@
// as the original value.
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
- Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
- EltTy);
+ Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
return true;
}
}
@@ -666,8 +663,7 @@
// Extract the run of set bits starting with bit zero, and test that the
// result is the same as the original value
if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
- Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
- EltTy);
+ Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
return true;
}
}
@@ -688,7 +684,7 @@
int32_t Log2 = (~ImmValue).exactLogBase2();
if (Log2 != -1) {
- Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
+ Imm = CurDAG->getTargetConstant(Log2, EltTy);
return true;
}
}
@@ -766,7 +762,7 @@
SDLoc DL(CN);
SDNode *RegOpnd;
SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
- DL, MVT::i64);
+ MVT::i64);
// The first instruction can be a LUi which is different from other
// instructions (ADDiu, ORI and SLL) in that it does not have a register
@@ -781,7 +777,7 @@
// The remaining instructions in the sequence are handled here.
for (++Inst; Inst != Seq.end(); ++Inst) {
- ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
+ ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
MVT::i64);
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
SDValue(RegOpnd, 0), ImmOpnd);
@@ -852,7 +848,7 @@
}
SDNode *Rdhwr =
- CurDAG->getMachineNode(RdhwrOpc, DL,
+ CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
Node->getValueType(0),
CurDAG->getRegister(Mips::HWR29, MVT::i32));
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
@@ -915,10 +911,10 @@
if (!SplatValue.isSignedIntN(10))
return std::make_pair(false, nullptr);
- SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
+ SDValue Imm = CurDAG->getTargetConstant(SplatValue,
ViaVecTy.getVectorElementType());
- SDNode *Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
+ SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
if (ResVecTy != ViaVecTy) {
// If LdiOp is writing to a different register class to ResVecTy, then
@@ -928,9 +924,9 @@
const TargetLowering *TLI = getTargetLowering();
MVT ResVecTySimple = ResVecTy.getSimpleVT();
const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
- Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
+ Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
ResVecTy, SDValue(Res, 0),
- CurDAG->getTargetConstant(RC->getID(), DL,
+ CurDAG->getTargetConstant(RC->getID(),
MVT::i32));
}
@@ -953,7 +949,7 @@
// All memory constraints can at least accept raw pointers.
case InlineAsm::Constraint_i:
OutOps.push_back(Op);
- OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
+ OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false;
case InlineAsm::Constraint_m:
if (selectAddrRegImm16(Op, Base, Offset)) {
@@ -962,7 +958,7 @@
return false;
}
OutOps.push_back(Op);
- OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
+ OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false;
case InlineAsm::Constraint_R:
// The 'R' constraint is supposed to be much more complicated than this.
@@ -976,7 +972,7 @@
return false;
}
OutOps.push_back(Op);
- OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
+ OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false;
case InlineAsm::Constraint_ZC:
// ZC matches whatever the pref, ll, and sc instructions can handle for the
@@ -1003,7 +999,7 @@
}
// In all cases, 0-bit offsets are acceptable.
OutOps.push_back(Op);
- OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
+ OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false;
}
return true;
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index c273cfb..09ff4f9 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -800,7 +800,7 @@
// Return 0.
if (C == 0)
- return DAG.getConstant(0, DL, VT);
+ return DAG.getConstant(0, VT);
// Return x.
if (C == 1)
@@ -809,7 +809,7 @@
// If c is power of 2, return (shl x, log2(c)).
if (isPowerOf2_64(C))
return DAG.getNode(ISD::SHL, DL, VT, X,
- DAG.getConstant(Log2_64(C), DL, ShiftTy));
+ DAG.getConstant(Log2_64(C), ShiftTy));
unsigned Log2Ceil = Log2_64_Ceil(C);
uint64_t Floor = 1LL << Log2_64(C);
@@ -864,9 +864,8 @@
(SplatValue.getZExtValue() >= EltSize))
return SDValue();
- SDLoc DL(N);
- return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
- DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
+ return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
+ DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
}
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
@@ -1213,7 +1212,7 @@
Nd.getAlignment());
// i32 load from higher address.
- Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
+ Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
MachinePointerInfo(), Nd.isVolatile(),
Nd.isNonTemporal(), Nd.isInvariant(),
@@ -1238,9 +1237,9 @@
SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
EVT PtrVT = Ptr.getValueType();
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
- Val, DAG.getConstant(0, DL, MVT::i32));
+ Val, DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
- Val, DAG.getConstant(1, DL, MVT::i32));
+ Val, DAG.getConstant(1, MVT::i32));
if (!Subtarget.isLittle())
std::swap(Lo, Hi);
@@ -1251,7 +1250,7 @@
Nd.getAAInfo());
// i32 store to higher address.
- Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
+ Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
Nd.isVolatile(), Nd.isNonTemporal(),
std::min(Nd.getAlignment(), 4U), Nd.getAAInfo());
@@ -1284,9 +1283,9 @@
static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
- DAG.getConstant(0, DL, MVT::i32));
+ DAG.getConstant(0, MVT::i32));
SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
- DAG.getConstant(1, DL, MVT::i32));
+ DAG.getConstant(1, MVT::i32));
return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
}
@@ -1382,7 +1381,7 @@
SDValue LaneB = Op->getOperand(2);
if (ResVecTy == MVT::v2i64) {
- LaneA = DAG.getConstant(0, DL, MVT::i32);
+ LaneA = DAG.getConstant(0, MVT::i32);
ViaVecTy = MVT::v4i32;
} else
LaneA = LaneB;
@@ -1400,8 +1399,7 @@
}
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
- return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op),
- Op->getValueType(0));
+ return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
}
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
@@ -1417,7 +1415,7 @@
SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
- DAG.getConstant(32, DL, MVT::i32));
+ DAG.getConstant(32, MVT::i32));
SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
}
@@ -1453,9 +1451,8 @@
if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
- SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
- MVT::i32);
- SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
+ SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
+ SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
if (BigEndian)
std::swap(BitImmLoOp, BitImmHiOp);
@@ -1477,8 +1474,8 @@
Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
- Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
- Exp2Imm);
+ Exp2Imm =
+ DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
}
return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
@@ -1487,7 +1484,7 @@
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
EVT ResTy = Op->getValueType(0);
SDLoc DL(Op);
- SDValue One = DAG.getConstant(1, DL, ResTy);
+ SDValue One = DAG.getConstant(1, ResTy);
SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
@@ -1499,7 +1496,7 @@
EVT ResTy = Op->getValueType(0);
APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
<< cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
- SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
+ SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
}
@@ -1581,8 +1578,8 @@
APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
Op->getConstantOperandVal(3));
return DAG.getNode(ISD::VSELECT, DL, VecTy,
- DAG.getConstant(Mask, DL, VecTy, true),
- Op->getOperand(2), Op->getOperand(1));
+ DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
+ Op->getOperand(1));
}
case Intrinsic::mips_binsri_b:
case Intrinsic::mips_binsri_h:
@@ -1594,8 +1591,8 @@
APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
Op->getConstantOperandVal(3));
return DAG.getNode(ISD::VSELECT, DL, VecTy,
- DAG.getConstant(Mask, DL, VecTy, true),
- Op->getOperand(2), Op->getOperand(1));
+ DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
+ Op->getOperand(1));
}
case Intrinsic::mips_bmnz_v:
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
@@ -1616,7 +1613,7 @@
case Intrinsic::mips_bneg_w:
case Intrinsic::mips_bneg_d: {
EVT VecTy = Op->getValueType(0);
- SDValue One = DAG.getConstant(1, DL, VecTy);
+ SDValue One = DAG.getConstant(1, VecTy);
return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One,
@@ -1652,7 +1649,7 @@
case Intrinsic::mips_bset_w:
case Intrinsic::mips_bset_d: {
EVT VecTy = Op->getValueType(0);
- SDValue One = DAG.getConstant(1, DL, VecTy);
+ SDValue One = DAG.getConstant(1, VecTy);
return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One,
@@ -1926,7 +1923,7 @@
case Intrinsic::mips_insve_d:
return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
- DAG.getConstant(0, DL, MVT::i32));
+ DAG.getConstant(0, MVT::i32));
case Intrinsic::mips_ldi_b:
case Intrinsic::mips_ldi_h:
case Intrinsic::mips_ldi_w:
@@ -2366,7 +2363,7 @@
}
// SelectionDAG::getConstant will promote SplatValue appropriately.
- SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
+ SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
// Bitcast to the type we originally wanted
if (ViaVecTy != ResTy)
@@ -2388,7 +2385,7 @@
for (unsigned i = 0; i < NumElts; ++i) {
Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
Node->getOperand(i),
- DAG.getConstant(i, DL, MVT::i32));
+ DAG.getConstant(i, MVT::i32));
}
return Vector;
}
@@ -2458,9 +2455,8 @@
Imm |= Idx & 0x3;
}
- SDLoc DL(Op);
- return DAG.getNode(MipsISD::SHF, DL, ResTy,
- DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
+ return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
+ DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
}
// Lower VECTOR_SHUFFLE into ILVEV (if possible).
@@ -2669,7 +2665,7 @@
for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
++I)
- Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
+ Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);