R600: Expand mul24 for GPUs without it
llvm-svn: 209458
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.umul24.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.umul24.ll
index 21f824a..72a3602 100644
--- a/llvm/test/CodeGen/R600/llvm.AMDGPU.umul24.ll
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.umul24.ll
@@ -1,11 +1,17 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
+; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
declare i32 @llvm.AMDGPU.umul24(i32, i32) nounwind readnone
-; SI-LABEL: @test_umul24
+; FUNC-LABEL: @test_umul24
+; SI: V_MUL_U32_U24
+; R600: MUL_UINT24
+; R600: MULLO_UINT
define void @test_umul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
%mul = call i32 @llvm.AMDGPU.umul24(i32 %src0, i32 %src1) nounwind readnone
store i32 %mul, i32 addrspace(1)* %out, align 4
ret void
}
-