CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
Two issues found when doing codegen for splitting vector with non-zero alloca addr space:
DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT/SplitVecOp_EXTRACT_VECTOR_ELT uses dummy pointer info for creating
SDStore. Since one pointer operand contains multiply and add, InferPointerInfo is unable to
infer the correct pointer info, which ends up with a dummy pointer info for the target to lower
store and results in isel failure. The fix is to introduce MachinePointerInfo::getUnknownStack to
represent MachinePointerInfo which is known in alloca address space but without other information.
TargetLowering::getVectorElementPointer uses value type of pointer in addr space 0 for
multiplication of index and then add it to the pointer. However the pointer may be in an addr
space which has different size than addr space 0. The fix is to use the pointer value type for
index multiplication.
Differential Revision: https://reviews.llvm.org/D39758
llvm-svn: 319622
diff --git a/llvm/test/CodeGen/AMDGPU/extload-align.ll b/llvm/test/CodeGen/AMDGPU/extload-align.ll
index 12cf27b..097ea2f 100644
--- a/llvm/test/CodeGen/AMDGPU/extload-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/extload-align.ll
@@ -1,4 +1,5 @@
-; RUN: llc -debug-only=machine-scheduler -march=amdgcn -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s
+; RUN: llc -debug-only=machine-scheduler -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s
+target datalayout = "A5"
; REQUIRES: asserts
; Verify that the extload generated from %eval has the default
@@ -6,18 +7,18 @@
; size and not 4 corresponding to the sign-extended size (i32).
; DEBUG: {{^}}# Machine code for function extload_align:
-; DEBUG: mem:LD2[<unknown>]{{[^(]}}
+; DEBUG: mem:LD2[<unknown>(addrspace=5)]{{[^(]}}
; DEBUG: {{^}}# End machine code for function extload_align.
-define amdgpu_kernel void @extload_align(i32* %out, i32 %index) #0 {
- %v0 = alloca [4 x i16]
- %a1 = getelementptr inbounds [4 x i16], [4 x i16]* %v0, i32 0, i32 0
- %a2 = getelementptr inbounds [4 x i16], [4 x i16]* %v0, i32 0, i32 1
- store i16 0, i16* %a1
- store i16 1, i16* %a2
- %a = getelementptr inbounds [4 x i16], [4 x i16]* %v0, i32 0, i32 %index
- %val = load i16, i16* %a
+define amdgpu_kernel void @extload_align(i32 addrspace(5)* %out, i32 %index) #0 {
+ %v0 = alloca [4 x i16], addrspace(5)
+ %a1 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 0
+ %a2 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 1
+ store i16 0, i16 addrspace(5)* %a1
+ store i16 1, i16 addrspace(5)* %a2
+ %a = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 %index
+ %val = load i16, i16 addrspace(5)* %a
%eval = sext i16 %val to i32
- store i32 %eval, i32* %out
+ store i32 %eval, i32 addrspace(5)* %out
ret void
}