| commit | 49506d78e7f437785f4d3f68063f4aa9c622bb2c | [log] [tgz] |
|---|---|---|
| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | Tue May 05 19:28:34 2015 +0000 |
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | Tue May 05 19:28:34 2015 +0000 |
| tree | 739e77ae549aaedcd76923e16478bc36747296cd | |
| parent | 80b3af7ab3f8e76507cc4491be1460f1b1d8adb2 [diff] |
[SystemZ] Add CodeGen support for scalar f64 ops in vector registers The z13 vector facility includes some instructions that operate only on the high f64 in a v2f64, effectively extending the FP register set from 16 to 32 registers. It's still better to use the old instructions if the operands happen to fit though, since the older instructions have a shorter encoding. Based on a patch by Richard Sandiford. llvm-svn: 236524