Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI
I looked into adding a warning / error for this to FileCheck, but there doesn't
seem to be a good way to avoid it triggering on the instances of it in RUN lines.
llvm-svn: 244481
diff --git a/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll b/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
index 4703d25..1a9074b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
@@ -13,8 +13,8 @@
; CHECK-NEXT: ldr [[BLOCKBASE:x[0-9]+]], {{\[}}[[ADDR]]]
; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]], w0, sxtw]
; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], w1, sxtw]
-; CHECK-NEXT cmp [[BLOCKVAL1]], [[BLOCKVAL2]]
-; CHECK-NEXT b.ne
+; CHECK-NEXT: cmp [[BLOCKVAL1]], [[BLOCKVAL2]]
+; CHECK-NEXT: b.ne
; Next BB
; CHECK: add [[BLOCKBASE2:x[0-9]+]], [[BLOCKBASE]], w1, sxtw
; CHECK-NEXT: add [[BLOCKBASE1:x[0-9]+]], [[BLOCKBASE]], w0, sxtw
diff --git a/llvm/test/CodeGen/AArch64/arm64-popcnt.ll b/llvm/test/CodeGen/AArch64/arm64-popcnt.ll
index d6c9471..9ee53a0 100644
--- a/llvm/test/CodeGen/AArch64/arm64-popcnt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-popcnt.ll
@@ -59,7 +59,7 @@
%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %cnt
; CHECK-LABEL: cnt32:
-; CHECK-NOT 16b
+; CHECK-NOT: 16b
; CHECK: ret
}
@@ -67,7 +67,7 @@
%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
ret i64 %cnt
; CHECK-LABEL: cnt64:
-; CHECK-NOT 16b
+; CHECK-NOT: 16b
; CHECK: ret
}
diff --git a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
index 9917421..614966d 100644
--- a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
+++ b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
@@ -62,7 +62,7 @@
; ...
; CHECK-NOT: add sp,
; CHECK: vpop {d6, d7, d8, d9}
-; CHECKL pop {r[[GLOBREG]], pc}
+; CHECK: pop {r[[GLOBREG]], pc}
; iOS uses aligned NEON stores here, which is convenient since we
; want to make sure that works too.
diff --git a/llvm/test/CodeGen/NVPTX/vector-call.ll b/llvm/test/CodeGen/NVPTX/vector-call.ll
index a03d7fd..968d1d4 100644
--- a/llvm/test/CodeGen/NVPTX/vector-call.ll
+++ b/llvm/test/CodeGen/NVPTX/vector-call.ll
@@ -4,7 +4,7 @@
declare void @bar(<4 x i32>)
-; CHECK-LABEL @foo
+; CHECK-LABEL: @foo
define void @foo(<4 x i32> %a) {
; CHECK: st.param.v4.b32
tail call void @bar(<4 x i32> %a)
diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
index ad8ed38..0280063 100644
--- a/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
@@ -10,7 +10,7 @@
}
; CHECK-LABEL: @main
-; CHECK-DAG li 4, 0
+; CHECK-DAG: li 4, 0
; CHECK-DAG: crxor 6, 6, 6
; CHECK: bl printf
diff --git a/llvm/test/CodeGen/PowerPC/rm-zext.ll b/llvm/test/CodeGen/PowerPC/rm-zext.ll
index 97c546c..df5fe4f 100644
--- a/llvm/test/CodeGen/PowerPC/rm-zext.ll
+++ b/llvm/test/CodeGen/PowerPC/rm-zext.ll
@@ -9,7 +9,7 @@
%shr2 = lshr i32 %mul, 5
ret i32 %shr2
-; CHECK-LABEL @foo
+; CHECK-LABEL: @foo
; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
; CHECK: blr
}
@@ -23,7 +23,7 @@
%or = or i32 %shr, %shl
ret i32 %or
-; CHECK-LABEL @test6
+; CHECK-LABEL: @test6
; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
; CHECK: blr
}
@@ -34,7 +34,7 @@
%cond = select i1 %cmp, i32 %a, i32 %b
ret i32 %cond
-; CHECK-LABEL @min
+; CHECK-LABEL: @min
; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
; CHECK: blr
}
diff --git a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll
index 5ec019d..d1f60da6 100644
--- a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll
+++ b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll
@@ -9,7 +9,7 @@
%div = sdiv i32 %a, 8
ret i32 %div
-; CHECK-LABEL @foo4
+; CHECK-LABEL: @foo4
; CHECK: srawi [[REG1:[0-9]+]], 3, 3
; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
; CHECK: extsw 3, [[REG2]]
@@ -22,12 +22,12 @@
%div = sdiv i64 %a, 8
ret i64 %div
-; CHECK-LABEL @foo8
+; CHECK-LABEL: @foo8
; CHECK: sradi [[REG1:[0-9]+]], 3, 3
; CHECK: addze 3, [[REG1]]
; CHECK: blr
-; CHECK-32-LABEL @foo8
+; CHECK-32-LABEL: @foo8
; CHECK-32-NOT: sradi
; CHECK-32: blr
}
@@ -58,7 +58,7 @@
; CHECK: neg 3, [[REG2]]
; CHECK: blr
-; CHECK-32-LABEL @foo8n
+; CHECK-32-LABEL: @foo8n
; CHECK-32-NOT: sradi
; CHECK-32: blr
}
diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
index f7ebf47..9e79b52 100644
--- a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
@@ -14,7 +14,7 @@
%result = add <1 x i128> %x, <i128 1>
ret <1 x i128> %result
; CHECK-LABEL: @increment_by_one
-; CHECK vadduqm 2, 2, 3
+; CHECK: vadduqm 2, 2, 3
}
define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
@@ -37,7 +37,7 @@
%result = sub <1 x i128> %x, <i128 1>
ret <1 x i128> %result
; CHECK-LABEL: @decrement_by_one
-; CHECK vsubuqm 2, 2, 3
+; CHECK: vsubuqm 2, 2, 3
}
define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
@@ -46,7 +46,7 @@
%result = sub <1 x i128> %x, %tmpvec2
ret <1 x i128> %result
; CHECK-LABEL: @decrement_by_val
-; CHECK vsubuqm 2, 2, 3
+; CHECK: vsubuqm 2, 2, 3
}
declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
diff --git a/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll b/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll
index a3583d4..9ec9b8b 100644
--- a/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll
+++ b/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll
@@ -17,12 +17,12 @@
; CHECK: .note.gc
; CHECK-NEXT: .align 8
; safe point count
-; CHECK .short 1
-; CHECK .long .Ltmp0
+; CHECK: .short 1
+; CHECK: .long .Ltmp0
; stack frame size (in words)
-; CHECK .short -1
+; CHECK: .short -1
; stack arity (arguments on the stack)
-; CHECK .short 0
+; CHECK: .short 0
; live root count
-; CHECK .short 0
+; CHECK: .short 0
diff --git a/llvm/test/CodeGen/X86/codegen-prepare-cast.ll b/llvm/test/CodeGen/X86/codegen-prepare-cast.ll
index 1ab8017..c5c2d64 100644
--- a/llvm/test/CodeGen/X86/codegen-prepare-cast.ll
+++ b/llvm/test/CodeGen/X86/codegen-prepare-cast.ll
@@ -11,7 +11,7 @@
; CHECK-LABEL: @_Dmain
; CHECK: load i8, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0)
-; CHECK ret
+; CHECK: ret
define fastcc i32 @_Dmain(%"char[][]" %unnamed) {
entry:
%tmp = getelementptr [7 x i8], [7 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1]
diff --git a/llvm/test/CodeGen/X86/fma-do-not-commute.ll b/llvm/test/CodeGen/X86/fma-do-not-commute.ll
index 1f6a19c..89be079 100644
--- a/llvm/test/CodeGen/X86/fma-do-not-commute.ll
+++ b/llvm/test/CodeGen/X86/fma-do-not-commute.ll
@@ -6,7 +6,7 @@
; CHECK-LABEL: test1:
; %arg lives in xmm0 and it shouldn't be redefined until it is used in the FMA.
-; CHECK-NOT {{.*}}, %xmm0
+; CHECK-NOT: {{.*}}, %xmm0
; %addr lives in rdi.
; %addr2 lives in rsi.
; CHECK: vmovss (%rsi), [[ADDR2:%xmm[0-9]+]]
diff --git a/llvm/test/CodeGen/X86/machine-cp.ll b/llvm/test/CodeGen/X86/machine-cp.ll
index aaed0f0..768b9ca 100644
--- a/llvm/test/CodeGen/X86/machine-cp.ll
+++ b/llvm/test/CodeGen/X86/machine-cp.ll
@@ -83,12 +83,12 @@
; CHECK-NOT: , [[CPY1]]
; CHECK: punpcklbw [[CPY2]], [[CPY2]]
; CHECK-NEXT: punpckhwd [[CPY2]], [[CPY2]]
-; CHECK-NEXT pslld $31, [[CPY2]]
+; CHECK-NEXT: pslld $31, [[CPY2]]
; Check that CPY1 is not redefined.
; CHECK-NOT: , [[CPY1]]
; CHECK: punpcklbw [[CPY1]], [[CPY1]]
; CHECK-NEXT: punpcklwd [[CPY1]], [[CPY1]]
-; CHECK-NEXT pslld $31, [[CPY1]]
+; CHECK-NEXT: pslld $31, [[CPY1]]
define <16 x float> @foo(<16 x float> %x) {
bb:
%v3 = icmp slt <16 x i32> undef, zeroinitializer
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke.ll b/llvm/test/CodeGen/X86/statepoint-invoke.ll
index 81b9ab8..7e35d4f 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke.ll
+++ b/llvm/test/CodeGen/X86/statepoint-invoke.ll
@@ -113,7 +113,7 @@
normal_return:
; CHECK-LABEL: %normal_return
; CHECK: cmoveq {{.*}}[[REGVAL2]]{{.*}}
- ; CHECK retq
+ ; CHECK: retq
%a1 = phi i64 addrspace(1)* [%val1.relocated, %left.relocs], [%val3.relocated, %right.relocs]
%a2 = phi i64 addrspace(1)* [%val2.relocated_left, %left.relocs], [%val2.relocated_right, %right.relocs]
%ret = select i1 %cond, i64 addrspace(1)* %a1, i64 addrspace(1)* %a2