[RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.
* The method getRegAllocationHints() is now of bool type instead of void. If
true is returned, regalloc (AllocationOrder) will *only* try to allocate the
hints, as opposed to merely trying them before non-hinted registers.
* TargetRegisterInfo::getRegAllocationHints() is implemented for SystemZ with
an increase in number of LOCRs.
In this case, it is desired to force the hints even though there is a slight
increase in spilling, because if a non-hinted register would be allocated,
the LOCRMux pseudo would have to be expanded with a jump sequence. The LOCR
(Load On Condition) SystemZ instruction must have both operands in either the
low or high part of the 64 bit register.
Reviewers: Quentin Colombet and Ulrich Weigand
https://reviews.llvm.org/D36795
llvm-svn: 317879
diff --git a/llvm/lib/CodeGen/AllocationOrder.cpp b/llvm/lib/CodeGen/AllocationOrder.cpp
index d840a2f..3d10694 100644
--- a/llvm/lib/CodeGen/AllocationOrder.cpp
+++ b/llvm/lib/CodeGen/AllocationOrder.cpp
@@ -31,11 +31,12 @@
const VirtRegMap &VRM,
const RegisterClassInfo &RegClassInfo,
const LiveRegMatrix *Matrix)
- : Pos(0) {
+ : Pos(0), HardHints(false) {
const MachineFunction &MF = VRM.getMachineFunction();
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
- TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
+ if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
+ HardHints = true;
rewind();
DEBUG({
diff --git a/llvm/lib/CodeGen/AllocationOrder.h b/llvm/lib/CodeGen/AllocationOrder.h
index 8223a52..467bcc2 100644
--- a/llvm/lib/CodeGen/AllocationOrder.h
+++ b/llvm/lib/CodeGen/AllocationOrder.h
@@ -32,7 +32,11 @@
ArrayRef<MCPhysReg> Order;
int Pos;
+ // If HardHints is true, *only* Hints will be returned.
+ bool HardHints;
+
public:
+
/// Create a new AllocationOrder for VirtReg.
/// @param VirtReg Virtual register to allocate for.
/// @param VRM Virtual register map for function.
@@ -51,6 +55,8 @@
unsigned next(unsigned Limit = 0) {
if (Pos < 0)
return Hints.end()[Pos++];
+ if (HardHints)
+ return 0;
if (!Limit)
Limit = Order.size();
while (Pos < int(Limit)) {
@@ -68,6 +74,8 @@
unsigned nextWithDups(unsigned Limit) {
if (Pos < 0)
return Hints.end()[Pos++];
+ if (HardHints)
+ return 0;
if (Pos < int(Limit))
return Order[Pos++];
return 0;
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 758fdab..eb8bcc3 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -360,7 +360,7 @@
}
// Compute target-independent register allocator hints to help eliminate copies.
-void
+bool
TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
@@ -382,17 +382,18 @@
// Check that Phys is a valid hint in VirtReg's register class.
if (!isPhysicalRegister(Phys))
- return;
+ return false;
if (MRI.isReserved(Phys))
- return;
+ return false;
// Check that Phys is in the allocation order. We shouldn't heed hints
// from VirtReg's register class if they aren't in the allocation order. The
// target probably has a reason for removing the register.
if (!is_contained(Order, Phys))
- return;
+ return false;
// All clear, tell the register allocator to prefer this register.
Hints.push_back(Phys);
+ return false;
}
bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {