[IPRA][ARM] Disable no-CSR optimisation for ARM
This optimisation isn't generally profitable for ARM, because we can
save/restore many registers in the prologue and epilogue using the PUSH
and POP instructions, but mostly use individual LDR/STR instructions for
other spills.
Differential revision: https://reviews.llvm.org/D64910
llvm-svn: 367670
diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
index 878c9ff..284f7ba 100644
--- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
@@ -378,6 +378,11 @@
return true;
}
+ /// Check if the no-CSR optimisation is profitable for the given function.
+ virtual bool isProfitableForNoCSROpt(const Function &F) const {
+ return true;
+ }
+
/// Return initial CFA offset value i.e. the one valid at the beginning of the
/// function (before any stack operations).
virtual int getInitialCFAOffset(const MachineFunction &MF) const;
diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp
index 64552b5..757ff0e 100644
--- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp
+++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp
@@ -171,7 +171,8 @@
SetRegAsDefined(PReg);
}
- if (TargetFrameLowering::isSafeForNoCSROpt(F)) {
+ if (TargetFrameLowering::isSafeForNoCSROpt(F) &&
+ MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) {
++NumCSROpt;
LLVM_DEBUG(dbgs() << MF.getName()
<< " function optimized for not having CSR.\n");
diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
index 9c4483c..c5cd87b 100644
--- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
+++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
@@ -71,7 +71,9 @@
// When interprocedural register allocation is enabled caller saved registers
// are preferred over callee saved registers.
- if (MF.getTarget().Options.EnableIPRA && isSafeForNoCSROpt(MF.getFunction()))
+ if (MF.getTarget().Options.EnableIPRA &&
+ isSafeForNoCSROpt(MF.getFunction()) &&
+ isProfitableForNoCSROpt(MF.getFunction()))
return;
// Get the callee saved register list...
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h
index 7544ca3..6d8aee5 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.h
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.h
@@ -63,6 +63,11 @@
bool enableShrinkWrapping(const MachineFunction &MF) const override {
return true;
}
+ bool isProfitableForNoCSROpt(const Function &F) const override {
+ // The no-CSR optimisation is bad for code size on ARM, because we can save
+ // many registers with a single PUSH/POP pair.
+ return false;
+ }
private:
void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
diff --git a/llvm/test/CodeGen/ARM/ipra-no-csr.ll b/llvm/test/CodeGen/ARM/ipra-no-csr.ll
new file mode 100644
index 0000000..8070573
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ipra-no-csr.ll
@@ -0,0 +1,22 @@
+; RUN: llc -mtriple armv7a--none-eabi < %s | FileCheck %s
+; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s
+
+; Other targets disable callee-saved registers for internal functions when
+; using IPRA, but that isn't profitable for ARM because the PUSH/POP
+; instructions can more efficiently save registers than using individual
+; LDR/STRs in the caller.
+
+define internal void @callee() norecurse {
+; CHECK-LABEL: callee:
+entry:
+; CHECK: push {r4, lr}
+; CHECK: pop {r4, pc}
+ tail call void asm sideeffect "", "~{r4}"()
+ ret void
+}
+
+define void @caller() {
+entry:
+ call void @callee()
+ ret void
+}