| commit | 4b5462f1194ee3d6bf7862d0ad70159b5a27eced | [log] [tgz] |
|---|---|---|
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | Sun Apr 24 18:35:59 2016 +0000 |
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | Sun Apr 24 18:35:59 2016 +0000 |
| tree | 83ee5f5c884ba21134203b7ed9f4f3d14e476b1d | |
| parent | bfccefd5142626be523fd1a668566512553b0b59 [diff] |
[InstCombine][SSE] Reduce DIVSS/DIVSD to FDIV if only first element is required As discussed on D19318, if we only demand the first element of a DIVSS/DIVSD intrinsic, then reduce to a FDIV call. This matches the existing FADD/FSUB/FMUL patterns. llvm-svn: 267359