commit 4c8f634f23b3910d1915103ac2249ce08ae407bc
author Hal Finkel <hfinkel@anl.gov> Mon Mar 31 17:02:10 2014 +0000
committer Hal Finkel <hfinkel@anl.gov> Mon Mar 31 17:02:10 2014 +0000
tree 368680857a94bd23b1e3208d6d5c58b370a90037
parent ed0e88c31ab2a57b5540b93621637b86903ee101

[PowerPC] Correct P7 dispatch unit allocation for vector instructions

llvm-svn: 205222

llvm/lib/Target/PowerPC/PPCScheduleP7.td

diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
index 04d37e4..d3e4269 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
@@ -339,36 +339,28 @@
                                                   P7_DU3, P7_DU4], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [5, 1, 1]>,
-  InstrItinData<IIC_VecGeneral  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecGeneral  , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [2, 1, 1]>,
-  InstrItinData<IIC_VecVSL      , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecVSL      , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [2, 1, 1]>,
-  InstrItinData<IIC_VecVSR      , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecVSR      , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [2, 1, 1]>,
-  InstrItinData<IIC_VecFP       , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecFP       , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [6, 1, 1]>,
-  InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [6, 1, 1]>,
-  InstrItinData<IIC_VecFPRound  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecFPRound  , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1, P7_VS2]>],
                                   [6, 1, 1]>,
-  InstrItinData<IIC_VecComplex  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecComplex  , [InstrStage<1, [P7_DU1], 0>,
                                    InstrStage<1, [P7_VS1]>],
                                   [7, 1, 1]>,
-  InstrItinData<IIC_VecPerm     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
+  InstrItinData<IIC_VecPerm     , [InstrStage<1, [P7_DU1, P7_DU2], 0>,
                                    InstrStage<1, [P7_VS2]>],
                                   [3, 1, 1]>
 ]>;