commit 4d302f6911f510153a026274b21eb9fb2c260903
author Alexander Timofeev <Alexander.Timofeev@amd.com> Thu Sep 13 09:06:56 2018 +0000
committer Alexander Timofeev <Alexander.Timofeev@amd.com> Thu Sep 13 09:06:56 2018 +0000
tree bdc75e185b3ad01b7e91dbb670b2346d3e8ffc26
parent c49da2e4ed44c74473407353bc0bf72fb61c8664

    [AMDGPU] Load divergence predicate refactoring

    Differential revision: https://reviews.llvm.org/D51931

    Reviewers: rampitec

llvm-svn: 342120

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index d689d92..97d4db4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -102,6 +102,7 @@
   bool isNoNanSrc(SDValue N) const;
   bool isInlineImmediate(const SDNode *N) const;
   bool isVGPRImm(const SDNode *N) const;
+  bool isUniformLoad(const SDNode *N) const;
   bool isUniformBr(const SDNode *N) const;
 
   MachineSDNode *buildSMovImm64(SDLoc &DL, uint64_t Val, EVT VT) const;
@@ -2117,6 +2118,30 @@
   return !AllUsesAcceptSReg && (Limit < 10);
 }
 
+bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode * N) const {
+  auto Ld = cast<LoadSDNode>(N);
+
+  return Ld->getAlignment() >= 4 &&
+        (
+          (
+            (
+              Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS       ||
+              Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT
+            )
+            &&
+            !N->isDivergent()
+          )
+          ||
+          (
+            Subtarget->getScalarizeGlobalBehavior() &&
+            Ld->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
+            !Ld->isVolatile() &&
+            !N->isDivergent() &&
+            static_cast<const SITargetLowering *>(
+              getTargetLowering())->isMemOpHasNoClobberedMemOperand(N)
+          )
+        );
+}
 
 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
   const AMDGPUTargetLowering& Lowering =