commit 4d94d4d5f7c82a543cebe0b7413aa9b0b90ae6ec
author Igor Breger <igor.breger@intel.com> Sun Mar 06 12:38:58 2016 +0000
committer Igor Breger <igor.breger@intel.com> Sun Mar 06 12:38:58 2016 +0000
tree 0a21c7b531228a0ac9a00a0b3ac4a1f95311ccd6
parent c0531a4a21e809397b84ea89bd3a6ba5abbcfdc0

AVX512BW: Support llvm intrinsic masked vector load/store for i8/i16 element types on SKX

Differential Revision: http://reviews.llvm.org/D17913

llvm-svn: 262803

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 397a0f2..efa7feb 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1438,7 +1438,8 @@
   int DataWidth = isa<PointerType>(ScalarTy) ?
     DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits();
 
-  return (DataWidth >= 32 && ST->hasAVX());
+  return (DataWidth >= 32 && ST->hasAVX()) ||
+         (DataWidth >= 8 && ST->hasBWI());
 }
 
 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) {