commit 4f79f96fd7351a0bb731fcb508f76e6ab4ae2134
author Kit Barton <kbarton@ca.ibm.com> Tue Jun 16 16:01:15 2015 +0000
committer Kit Barton <kbarton@ca.ibm.com> Tue Jun 16 16:01:15 2015 +0000
tree b9dc7c9b94cbb3e5b67d8652bca6ce19d941bed8
parent 6fea1af01add7a54251d037c99a7d6deb1814184

Properly handle the mftb instruction.

The mftb instruction was incorrectly marked as deprecated in the PPC
Backend. Instead, it should not be treated as deprecated, but rather be
implemented using the mfspr instruction. A similar patch was put into GCC last
year. Details can be found at:

https://sourceware.org/ml/binutils/2014-11/msg00383.html.
This change will replace instances of the mftb instruction with the mfspr
instruction for all CPUs except 601 and pwr3. This will also be the default
behaviour.

Additional details can be found in:

https://llvm.org/bugs/show_bug.cgi?id=23680

Phabricator review: http://reviews.llvm.org/D10419

llvm-svn: 239827

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 1736d03..a699a55 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1184,6 +1184,13 @@
     Inst = TmpInst;
     break;
   }
+  case PPC::MFTB: {
+    if (STI.getFeatureBits()[PPC::FeatureMFTB]) {
+      assert(Inst.getNumOperands() == 2 && "Expecting two operands");
+      Inst.setOpcode(PPC::MFSPR);
+    }
+    break;
+  }
   }
 }