X86: Don't emit SAHF/LAHF for 64-bit targets unless explicitly supported
These instructions are not supported by all CPUs in 64-bit mode. Emitting them
causes Chromium to crash on start-up for users with such chips.
(GCC puts these instructions behind -msahf on 64-bit for the same reason.)
This patch adds FeatureLAHFSAHF, enables it by default for 32-bit targets
and modern CPUs, and changes X86InstrInfo::copyPhysReg back to the lowering
from before r244503 when the instructions are not available.
Differential Revision: http://reviews.llvm.org/D15240
llvm-svn: 254793
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 7d9f396..dc5ab1b 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -182,6 +182,8 @@
"Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
"Support RDSEED instruction">;
+def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
+ "Support LAHF and SAHF instructions">;
def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
"Support MPX instructions">;
def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
@@ -273,7 +275,8 @@
FeatureSSSE3,
FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem
+ FeatureSlowBTMem,
+ FeatureLAHFSAHF
]>;
def : ProcessorModel<"penryn", SandyBridgeModel, [
FeatureSlowUAMem16,
@@ -281,7 +284,8 @@
FeatureSSE41,
FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem
+ FeatureSlowBTMem,
+ FeatureLAHFSAHF
]>;
// Atom CPUs.
@@ -299,7 +303,8 @@
FeatureSlowDivide64,
FeatureCallRegIndirect,
FeatureLEAUsesAG,
- FeaturePadShortFunctions
+ FeaturePadShortFunctions,
+ FeatureLAHFSAHF
]>;
def : BonnellProc<"bonnell">;
def : BonnellProc<"atom">; // Pin the generic name to the baseline.
@@ -319,7 +324,8 @@
FeaturePRFCHW,
FeatureSlowLEA,
FeatureSlowIncDec,
- FeatureSlowBTMem
+ FeatureSlowBTMem,
+ FeatureLAHFSAHF
]>;
def : SilvermontProc<"silvermont">;
def : SilvermontProc<"slm">; // Legacy alias.
@@ -331,7 +337,8 @@
FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
- FeaturePOPCNT
+ FeaturePOPCNT,
+ FeatureLAHFSAHF
]>;
def : NehalemProc<"nehalem">;
def : NehalemProc<"corei7">;
@@ -346,7 +353,8 @@
FeatureSlowBTMem,
FeaturePOPCNT,
FeatureAES,
- FeaturePCLMUL
+ FeaturePCLMUL,
+ FeatureLAHFSAHF
]>;
def : WestmereProc<"westmere">;
@@ -363,7 +371,8 @@
FeatureAES,
FeaturePCLMUL,
FeatureXSAVE,
- FeatureXSAVEOPT
+ FeatureXSAVEOPT,
+ FeatureLAHFSAHF
]>;
def : SandyBridgeProc<"sandybridge">;
def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
@@ -382,7 +391,8 @@
FeatureXSAVEOPT,
FeatureRDRAND,
FeatureF16C,
- FeatureFSGSBase
+ FeatureFSGSBase,
+ FeatureLAHFSAHF
]>;
def : IvyBridgeProc<"ivybridge">;
def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
@@ -408,7 +418,8 @@
FeatureFMA,
FeatureRTM,
FeatureHLE,
- FeatureSlowIncDec
+ FeatureSlowIncDec,
+ FeatureLAHFSAHF
]>;
def : HaswellProc<"haswell">;
def : HaswellProc<"core-avx2">; // Legacy alias.
@@ -436,7 +447,8 @@
FeatureHLE,
FeatureADX,
FeatureRDSEED,
- FeatureSlowIncDec
+ FeatureSlowIncDec,
+ FeatureLAHFSAHF
]>;
def : BroadwellProc<"broadwell">;
@@ -465,7 +477,8 @@
FeatureRTM,
FeatureHLE,
FeatureSlowIncDec,
- FeatureMPX
+ FeatureMPX,
+ FeatureLAHFSAHF
]>;
def : KnightsLandingProc<"knl">;
@@ -500,7 +513,8 @@
FeatureSlowIncDec,
FeatureMPX,
FeatureXSAVEC,
- FeatureXSAVES
+ FeatureXSAVES,
+ FeatureLAHFSAHF
]>;
def : SkylakeProc<"skylake">;
def : SkylakeProc<"skx">; // Legacy alias.
@@ -547,7 +561,7 @@
FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"barcelona", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
// Bobcat
def : Proc<"btver1", [
@@ -560,7 +574,8 @@
FeatureLZCNT,
FeaturePOPCNT,
FeatureXSAVE,
- FeatureSlowSHLD
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Jaguar
@@ -580,7 +595,8 @@
FeaturePOPCNT,
FeatureXSAVE,
FeatureXSAVEOPT,
- FeatureSlowSHLD
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Bulldozer
@@ -598,7 +614,8 @@
FeatureLZCNT,
FeaturePOPCNT,
FeatureXSAVE,
- FeatureSlowSHLD
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Piledriver
def : Proc<"bdver2", [
@@ -619,7 +636,8 @@
FeatureBMI,
FeatureTBM,
FeatureFMA,
- FeatureSlowSHLD
+ FeatureSlowSHLD,
+ FeatureLAHFSAHF
]>;
// Steamroller
@@ -643,7 +661,8 @@
FeatureFMA,
FeatureXSAVEOPT,
FeatureSlowSHLD,
- FeatureFSGSBase
+ FeatureFSGSBase,
+ FeatureLAHFSAHF
]>;
// Excavator
@@ -666,7 +685,8 @@
FeatureTBM,
FeatureFMA,
FeatureXSAVEOPT,
- FeatureFSGSBase
+ FeatureFSGSBase,
+ FeatureLAHFSAHF
]>;
def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2cf1d4b..c07bca8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -13930,6 +13930,9 @@
SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
DAG.getConstant(8, dl, MVT::i8));
SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
+
+ // Some 64-bit targets lack SAHF support, but they do support FCOMI.
+ assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index e9d36f8..ebe3290 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4385,7 +4385,32 @@
int Reg = FromEFLAGS ? DestReg : SrcReg;
bool is32 = X86::GR32RegClass.contains(Reg);
bool is64 = X86::GR64RegClass.contains(Reg);
+
if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
+ int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
+ int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
+ int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
+ int Pop = is64 ? X86::POP64r : X86::POP32r;
+ int PopF = is64 ? X86::POPF64 : X86::POPF32;
+ int AX = is64 ? X86::RAX : X86::EAX;
+
+ if (!Subtarget.hasLAHFSAHF()) {
+ assert(is64 && "Not having LAHF/SAHF only happens on 64-bit.");
+ // Moving EFLAGS to / from another register requires a push and a pop.
+ // Notice that we have to adjust the stack if we don't want to clobber the
+ // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
+ if (FromEFLAGS) {
+ BuildMI(MBB, MI, DL, get(PushF));
+ BuildMI(MBB, MI, DL, get(Pop), DestReg);
+ }
+ if (ToEFLAGS) {
+ BuildMI(MBB, MI, DL, get(Push))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ BuildMI(MBB, MI, DL, get(PopF));
+ }
+ return;
+ }
+
// The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
// inefficient. Instead:
// - Save the overflow flag OF into AL using SETO, and restore it using a
@@ -4407,10 +4432,6 @@
// Notice that we have to adjust the stack if we don't want to clobber the
// first frame index. See X86FrameLowering.cpp - clobbersTheStack.
- int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
- int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
- int Pop = is64 ? X86::POP64r : X86::POP32r;
- int AX = is64 ? X86::RAX : X86::EAX;
bool AXDead = (Reg == AX);
// FIXME: The above could figure out that AX is dead in more cases with:
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 1e66739..1c21a09 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -799,6 +799,7 @@
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
+def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">;
def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
def HasMPX : Predicate<"Subtarget->hasMPX()">;
@@ -1502,10 +1503,12 @@
let SchedRW = [WriteALU] in {
let Defs = [EFLAGS], Uses = [AH] in
def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
- [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
+ [(set EFLAGS, (X86sahf AH))], IIC_AHF>,
+ Requires<[HasLAHFSAHF]>;
let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
- IIC_AHF>; // AH = flags
+ IIC_AHF>, // AH = flags
+ Requires<[HasLAHFSAHF]>;
} // SchedRW
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index 44a46b7..f90a0b0 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -189,6 +189,15 @@
FullFS = "+64bit,+sse2";
}
+ // LAHF/SAHF are always supported in non-64-bit mode.
+ if (!In64BitMode) {
+ if (!FullFS.empty())
+ FullFS = "+sahf," + FullFS;
+ else
+ FullFS = "+sahf";
+ }
+
+
// Parse features string and set the CPU.
ParseSubtargetFeatures(CPUName, FullFS);
@@ -264,6 +273,7 @@
HasSHA = false;
HasPRFCHW = false;
HasRDSEED = false;
+ HasLAHFSAHF = false;
HasMPX = false;
IsBTMemSlow = false;
IsSHLDSlow = false;
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 353b4f7..83bc640 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -152,6 +152,9 @@
/// Processor has RDSEED instructions.
bool HasRDSEED;
+ /// Processor has LAHF/SAHF instructions.
+ bool HasLAHFSAHF;
+
/// True if BT (bit test) of memory instructions are slow.
bool IsBTMemSlow;
@@ -374,6 +377,7 @@
bool hasSHA() const { return HasSHA; }
bool hasPRFCHW() const { return HasPRFCHW; }
bool hasRDSEED() const { return HasRDSEED; }
+ bool hasLAHFSAHF() const { return HasLAHFSAHF; }
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isSHLDSlow() const { return IsSHLDSlow; }
bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }