commit 5035ee0212180c67eee84d2ab2f966e687cb3171
author Amara Emerson <amara.emerson@arm.com> Mon Oct 07 16:55:23 2013 +0000
committer Amara Emerson <amara.emerson@arm.com> Mon Oct 07 16:55:23 2013 +0000
tree 10ab5b62f58fd4dc6023da99e117813fc7555dcb
parent 20594a842cbb4f66e3f67600b2f80200032e6734

[ARM] Improve build attributes emission.

llvm-svn: 192111

llvm/lib/Target/ARM/ARMSubtarget.cpp

diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 3b34a2b..02d9387 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -76,6 +76,7 @@
   HasV5TOps = false;
   HasV5TEOps = false;
   HasV6Ops = false;
+  HasV6MOps = false;
   HasV6T2Ops = false;
   HasV7Ops = false;
   HasV8Ops = false;
@@ -158,7 +159,7 @@
   // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
   // ARM version or CPU and then remove this.
   if (!HasV6T2Ops && hasThumb2())
-    HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
+    HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6MOps = HasV6T2Ops = true;
 
   // Keep a pointer to static instruction cost data for the specified CPU.
   SchedModel = getSchedModelForCPU(CPUString);