commit 505f6b760d74af083087953f313effb10eb34253
author Nate Begeman <natebegeman@mac.com> Wed Apr 06 22:42:08 2005 +0000
committer Nate Begeman <natebegeman@mac.com> Wed Apr 06 22:42:08 2005 +0000
tree a10674404c45d9e942adfa50750d6ea379b69beb
parent 7ca0947274ef5eb4352ca73c24f1156f9b2b63cd

Fix some shift bugs

llvm-svn: 21126

llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp

diff --git a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 80c554c..4a318b2 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -2779,8 +2779,13 @@
             .addImm(32-Amount).addImm(Amount).addImm(31);
           BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg)
             .addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1);
-          BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
-            .addImm(32-Amount).addImm(Amount).addImm(31);
+          if (isSigned) {
+            BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
+              .addImm(Amount);
+          } else {
+            BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
+              .addImm(32-Amount).addImm(Amount).addImm(31);
+          }
         }
       } else {                 // Shifting more than 32 bits
         Amount -= 32;
@@ -2805,7 +2810,11 @@
             BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
               .addReg(SrcReg);
           }
-          BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
+          if (isSigned)
+            BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
+              .addImm(31);
+          else
+            BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
         }
       }
     } else {