[llvm-exegesis][NFC] Remove extra `llvm::` qualifications.
Summary: Second patch: in the lib.
Reviewers: gchatelet
Subscribers: nemanjai, tschuett, MaskRay, mgrang, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68692
llvm-svn: 374158
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index a659278..f5cc88c 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -16,19 +16,19 @@
static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
switch (RegBitWidth) {
case 32:
- return llvm::AArch64::MOVi32imm;
+ return AArch64::MOVi32imm;
case 64:
- return llvm::AArch64::MOVi64imm;
+ return AArch64::MOVi64imm;
}
llvm_unreachable("Invalid Value Width");
}
// Generates instruction to load an immediate value into a register.
-static llvm::MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
- const llvm::APInt &Value) {
+static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
+ const APInt &Value) {
if (Value.getBitWidth() > RegBitWidth)
llvm_unreachable("Value must fit in the Register");
- return llvm::MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
+ return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
.addReg(Reg)
.addImm(Value.getZExtValue());
}
@@ -42,24 +42,23 @@
ExegesisAArch64Target() : ExegesisTarget(AArch64CpuPfmCounters) {}
private:
- std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
- unsigned Reg,
- const llvm::APInt &Value) const override {
- if (llvm::AArch64::GPR32RegClass.contains(Reg))
+ std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ const APInt &Value) const override {
+ if (AArch64::GPR32RegClass.contains(Reg))
return {loadImmediate(Reg, 32, Value)};
- if (llvm::AArch64::GPR64RegClass.contains(Reg))
+ if (AArch64::GPR64RegClass.contains(Reg))
return {loadImmediate(Reg, 64, Value)};
- llvm::errs() << "setRegTo is not implemented, results will be unreliable\n";
+ errs() << "setRegTo is not implemented, results will be unreliable\n";
return {};
}
- bool matchesArch(llvm::Triple::ArchType Arch) const override {
- return Arch == llvm::Triple::aarch64 || Arch == llvm::Triple::aarch64_be;
+ bool matchesArch(Triple::ArchType Arch) const override {
+ return Arch == Triple::aarch64 || Arch == Triple::aarch64_be;
}
- void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override {
+ void addTargetSpecificPasses(PassManagerBase &PM) const override {
// Function return is a pseudo-instruction that needs to be expanded
- PM.add(llvm::createAArch64ExpandPseudoPass());
+ PM.add(createAArch64ExpandPseudoPass());
}
};