Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Eric has replied and has demanded the patch be reverted.
llvm-svn: 247702
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 3a8556e..f5f1247 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -558,7 +558,7 @@
const Triple &TT = TM.getTargetTriple();
StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString();
- std::string ArchFS = ARM_MC::ParseARMTargetTuple(TargetTuple(TT), CPU);
+ std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
if (!FS.empty()) {
if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str();
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 0f20694..50e9e6a 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -81,7 +81,7 @@
ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const ARMBaseTargetMachine &TM, bool IsLittle)
- : ARMGenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
+ : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
TargetTriple(TT), Options(TM.Options), TM(TM),
FrameLowering(initializeFrameLowering(CPU, FS)),
@@ -159,8 +159,7 @@
// Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied
// based on the architecture version.
- std::string ArchFS =
- ARM_MC::ParseARMTargetTuple(TargetTuple(TargetTriple), CPUString);
+ std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
if (!FS.empty()) {
if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str();
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index ada3aa7d..1fe2dbe 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -779,49 +779,45 @@
MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU,
+ const Triple &TheTriple, StringRef CPU,
bool isLittle) {
- switch (TT.getObjectFormat()) {
+ switch (TheTriple.getObjectFormat()) {
default:
llvm_unreachable("unsupported object format");
- case TargetTuple::MachO: {
- MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName());
- return new ARMAsmBackendDarwin(T, TT, CS);
+ case Triple::MachO: {
+ MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
+ return new ARMAsmBackendDarwin(T, TheTriple, CS);
}
- case TargetTuple::COFF:
- assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported");
- return new ARMAsmBackendWinCOFF(T, TT);
- case TargetTuple::ELF:
- assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target");
- uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
- return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
+ case Triple::COFF:
+ assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
+ return new ARMAsmBackendWinCOFF(T, TheTriple);
+ case Triple::ELF:
+ assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
+ uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+ return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
}
}
MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, true);
}
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, false);
}
MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, true);
}
MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, false);
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
index ff00732..6b4abd5 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
@@ -23,7 +23,7 @@
bool isThumbMode; // Currently emitting Thumb code.
bool IsLittleEndian; // Big or little endian.
public:
- ARMAsmBackend(const Target &T, const TargetTuple &TT, bool IsLittle)
+ ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
: MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
isThumbMode(TT.getArchName().startswith("thumb")),
IsLittleEndian(IsLittle) {}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
index b25f0a1..a6206e3 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
@@ -18,7 +18,7 @@
class ARMAsmBackendDarwin : public ARMAsmBackend {
public:
const MachO::CPUSubTypeARM Subtype;
- ARMAsmBackendDarwin(const Target &T, const TargetTuple &TT,
+ ARMAsmBackendDarwin(const Target &T, const Triple &TT,
MachO::CPUSubTypeARM st)
: ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
HasDataInCodeSupport = true;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
index 84d3191..68b12ed 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
@@ -15,7 +15,7 @@
class ARMAsmBackendELF : public ARMAsmBackend {
public:
uint8_t OSABI;
- ARMAsmBackendELF(const Target &T, const TargetTuple &TT, uint8_t OSABI,
+ ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI,
bool IsLittle)
: ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
index d5783b1..170f59a 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
@@ -15,8 +15,8 @@
namespace {
class ARMAsmBackendWinCOFF : public ARMAsmBackend {
public:
- ARMAsmBackendWinCOFF(const Target &T, const TargetTuple &TT)
- : ARMAsmBackend(T, TT, true) {}
+ ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple)
+ : ARMAsmBackend(T, TheTriple, true) {}
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index b858f1f..a969d30 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -1361,7 +1361,7 @@
MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
const MCSubtargetInfo &STI) {
- const TargetTuple &TT = STI.getTargetTuple();
+ const Triple &TT = STI.getTargetTriple();
if (TT.isOSBinFormatELF())
return new ARMTargetELFStreamer(S);
return new ARMTargetStreamer(S);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
index 9074646..1ac08159 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
@@ -12,16 +12,16 @@
//===----------------------------------------------------------------------===//
#include "ARMMCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
void ARMMCAsmInfoDarwin::anchor() { }
-ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const TargetTuple &TT) {
- if ((TT.getArch() == TargetTuple::armeb) ||
- (TT.getArch() == TargetTuple::thumbeb))
+ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
+ if ((TheTriple.getArch() == Triple::armeb) ||
+ (TheTriple.getArch() == Triple::thumbeb))
IsLittleEndian = false;
Data64bitsDirective = nullptr;
@@ -40,9 +40,9 @@
void ARMELFMCAsmInfo::anchor() { }
-ARMELFMCAsmInfo::ARMELFMCAsmInfo(const TargetTuple &TT) {
- if ((TT.getArch() == TargetTuple::armeb) ||
- (TT.getArch() == TargetTuple::thumbeb))
+ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
+ if ((TheTriple.getArch() == Triple::armeb) ||
+ (TheTriple.getArch() == Triple::thumbeb))
IsLittleEndian = false;
// ".comm align is in bytes but .align is pow-2."
@@ -56,9 +56,9 @@
SupportsDebugInformation = true;
// Exceptions handling
- switch (TT.getOS()) {
- case TargetTuple::Bitrig:
- case TargetTuple::NetBSD:
+ switch (TheTriple.getOS()) {
+ case Triple::Bitrig:
+ case Triple::NetBSD:
ExceptionsType = ExceptionHandling::DwarfCFI;
break;
default:
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
index 8e121a5..5e54816 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
@@ -19,20 +19,20 @@
#include "llvm/MC/MCAsmInfoELF.h"
namespace llvm {
-class TargetTuple;
+class Triple;
class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
virtual void anchor();
public:
- explicit ARMMCAsmInfoDarwin(const TargetTuple &TT);
+ explicit ARMMCAsmInfoDarwin(const Triple &TheTriple);
};
class ARMELFMCAsmInfo : public MCAsmInfoELF {
void anchor() override;
public:
- explicit ARMELFMCAsmInfo(const TargetTuple &TT);
+ explicit ARMELFMCAsmInfo(const Triple &TT);
void setUseIntegratedAssembler(bool Value) override;
};
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index ba2b6b1..b885783 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -57,7 +57,7 @@
return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
}
bool isTargetMachO(const MCSubtargetInfo &STI) const {
- const TargetTuple &TT = STI.getTargetTuple();
+ const Triple &TT = STI.getTargetTriple();
return TT.isOSBinFormatMachO();
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index e2a26a7..21c9fc1 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -15,7 +15,7 @@
#include "ARMMCAsmInfo.h"
#include "ARMMCTargetDesc.h"
#include "InstPrinter/ARMInstPrinter.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrAnalysis.h"
@@ -130,16 +130,16 @@
#define GET_SUBTARGETINFO_MC_DESC
#include "ARMGenSubtargetInfo.inc"
-std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) {
- bool isThumb = TT.getArch() == TargetTuple::thumb ||
- TT.getArch() == TargetTuple::thumbeb;
+std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
+ bool isThumb =
+ TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
bool NoCPU = CPU == "generic" || CPU.empty();
std::string ARMArchFeature;
switch (TT.getSubArch()) {
default:
llvm_unreachable("invalid sub-architecture for ARM");
- case TargetTuple::ARMSubArch_v8:
+ case Triple::ARMSubArch_v8:
if (NoCPU)
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
@@ -150,7 +150,7 @@
// Use CPU to figure out the exact features
ARMArchFeature = "+v8";
break;
- case TargetTuple::ARMSubArch_v8_1a:
+ case Triple::ARMSubArch_v8_1a:
if (NoCPU)
// v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
@@ -161,7 +161,7 @@
// Use CPU to figure out the exact features
ARMArchFeature = "+v8.1a";
break;
- case TargetTuple::ARMSubArch_v7m:
+ case Triple::ARMSubArch_v7m:
isThumb = true;
if (NoCPU)
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
@@ -170,7 +170,7 @@
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
break;
- case TargetTuple::ARMSubArch_v7em:
+ case Triple::ARMSubArch_v7em:
if (NoCPU)
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
// FeatureT2XtPk, FeatureMClass
@@ -179,7 +179,7 @@
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
break;
- case TargetTuple::ARMSubArch_v7s:
+ case Triple::ARMSubArch_v7s:
if (NoCPU)
// v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
// Swift
@@ -188,7 +188,7 @@
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
break;
- case TargetTuple::ARMSubArch_v7:
+ case Triple::ARMSubArch_v7:
// v7 CPUs have lots of different feature sets. If no CPU is specified,
// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
// the "minimum" feature set and use CPU string to figure out the exact
@@ -200,13 +200,13 @@
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
break;
- case TargetTuple::ARMSubArch_v6t2:
+ case Triple::ARMSubArch_v6t2:
ARMArchFeature = "+v6t2";
break;
- case TargetTuple::ARMSubArch_v6k:
+ case Triple::ARMSubArch_v6k:
ARMArchFeature = "+v6k";
break;
- case TargetTuple::ARMSubArch_v6m:
+ case Triple::ARMSubArch_v6m:
isThumb = true;
if (NoCPU)
// v6m: FeatureNoARM, FeatureMClass
@@ -214,19 +214,19 @@
else
ARMArchFeature = "+v6";
break;
- case TargetTuple::ARMSubArch_v6:
+ case Triple::ARMSubArch_v6:
ARMArchFeature = "+v6";
break;
- case TargetTuple::ARMSubArch_v5te:
+ case Triple::ARMSubArch_v5te:
ARMArchFeature = "+v5te";
break;
- case TargetTuple::ARMSubArch_v5:
+ case Triple::ARMSubArch_v5:
ARMArchFeature = "+v5t";
break;
- case TargetTuple::ARMSubArch_v4t:
+ case Triple::ARMSubArch_v4t:
ARMArchFeature = "+v4t";
break;
- case TargetTuple::NoSubArch:
+ case Triple::NoSubArch:
break;
}
@@ -247,9 +247,9 @@
return ARMArchFeature;
}
-MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const TargetTuple &TT,
+MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
- std::string ArchFS = ARM_MC::ParseARMTargetTuple(TT, CPU);
+ std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
if (!FS.empty()) {
if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str();
@@ -266,23 +266,23 @@
return X;
}
-static MCRegisterInfo *createARMMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
MCRegisterInfo *X = new MCRegisterInfo();
InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
return X;
}
static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
- const TargetTuple &TT) {
+ const Triple &TheTriple) {
MCAsmInfo *MAI;
- if (TT.isOSDarwin() || TT.isOSBinFormatMachO())
- MAI = new ARMMCAsmInfoDarwin(TT);
- else if (TT.isWindowsMSVCEnvironment())
+ if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
+ MAI = new ARMMCAsmInfoDarwin(TheTriple);
+ else if (TheTriple.isWindowsMSVCEnvironment())
MAI = new ARMCOFFMCAsmInfoMicrosoft();
- else if (TT.isOSWindows())
+ else if (TheTriple.isOSWindows())
MAI = new ARMCOFFMCAsmInfoGNU();
else
- MAI = new ARMELFMCAsmInfo(TT);
+ MAI = new ARMELFMCAsmInfo(TheTriple);
unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
@@ -290,8 +290,7 @@
return MAI;
}
-static MCCodeGenInfo *createARMMCCodeGenInfo(const TargetTuple &TT,
- Reloc::Model RM,
+static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
@@ -303,11 +302,11 @@
return X;
}
-static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
+static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
MCAsmBackend &MAB, raw_pwrite_stream &OS,
MCCodeEmitter *Emitter, bool RelaxAll) {
return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
- TT.getArch() == TargetTuple::thumb);
+ T.getArch() == Triple::thumb);
}
static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
@@ -317,7 +316,7 @@
return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
}
-static MCInstPrinter *createARMMCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
@@ -327,7 +326,7 @@
return nullptr;
}
-static MCRelocationInfo *createARMMCRelocationInfo(const TargetTuple &TT,
+static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
MCContext &Ctx) {
if (TT.isOSBinFormatMachO())
return createARMMachORelocationInfo(Ctx);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
index 0619f30..fd30623 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
@@ -32,7 +32,7 @@
class MCTargetStreamer;
class StringRef;
class Target;
-class TargetTuple;
+class Triple;
class raw_ostream;
class raw_pwrite_stream;
@@ -40,11 +40,11 @@
extern Target TheARMBETarget, TheThumbBETarget;
namespace ARM_MC {
-std::string ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU);
+std::string ParseARMTriple(const Triple &TT, StringRef CPU);
/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry.
-MCSubtargetInfo *createARMMCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
+MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS);
}
@@ -65,22 +65,22 @@
MCContext &Ctx);
MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU,
+ const Triple &TT, StringRef CPU,
bool IsLittleEndian);
MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCAsmBackend *createThumbLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCAsmBackend *createThumbBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
// Construct a PE/COFF machine code streamer which will generate a PE/COFF
// object file.